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Registered: ‎12-10-2018

AXI4 Peripheral Lite slave Selftest error

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Dear,

 

We are trying to create a connection between the MicroBlaze CPU and our VHDL code and found the AXI4 peripheral creator. We created an AXI4 Lite slave ip core and modified some values to make it so that the registers that are changed by the MB CPU, are directly connected to our VHDL outputs/inputs.

 

Our test AXI4 peripheral had 3 registers (32 bit) and worked flawlessly. We then created a larger peripheral with 8 registers (32 bit) based on the exact same structure, just with more slv_regs but it doesn't work. The selftest reports "Error reading register value at address BASE_ADDRESS_LOW". Meaning that slv_reg0 fails.

Vivado did mentioned this which got me worried:

WARNING: [Synth 8-6014] Unused sequential element slv_reg0_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:227]
WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:228]
WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:229]
WARNING: [Synth 8-6014] Unused sequential element slv_reg3_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:230]
WARNING: [Synth 8-6014] Unused sequential element loc_addr_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:236]

 

Is the method that I am using to get a bridge between the MB and VHDL code valid? Or is there a more proper method? I couldn't find an official method within the AXI4 library.

I have included the IP core as a zip.

 

Thanks!

Kind regards,

 

Jonathan

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Registered: ‎05-21-2015

Re: AXI4 Peripheral Lite slave Selftest error

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@jawkover,

I understand your concerns completely.

I don't work for Xilinx, neither have I ever used MicroBlaze.  (I've been known for using the open source ZipCPU instead, with AutoFPGA has a system integrator.)  However, I have been critical of Xilinx for picking such a complicated bus to interface with.

Perhaps the best evidence that the AXI bus is difficult to work with is the fact that Xilinx's own demonstration cores don't necessarily follow the bus standard.  You can read my evaluation of their AXI-lite slave core here.  I have yet to post my evaluation of their AXI (full) slave core, but I've now counted several bugs within it as well.  I'm currently holding off on posting this evaluation to hear if Xilinx has any interest in it.  So far, all I've heard has been crickets.

I've already posted my own tutorial of how to write an AXI-lite slave that (works, and) achieves twice the performance of Xilinx's demonstration slave.  You can find a copy of my own AXI-lite slave here, and even the (broken) Xilinx slave I examined here.  A more recent post presents the most common problems I've seen in AXI code.

I hope that someone, perhaps an expert in AXI modules, could create an official bridge or explain how to create one that is stable and meant to be used.

While it's not official, I have created an AXI-lite to WB bridge that has been formally verified.  It's also been used successfully on an FPGA, and there's even a VHDL wrapper for it.  Feel free to check it out and see if it's useful to you at all.  I personally find WB interface much easier to use.

Dan

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Re: AXI4 Peripheral Lite slave Selftest error

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@jawkover,

I took the time this morning to apply a formal evaluation of your code.  I found only two basic issues, both associated with the code the peripheral creator generates, and neither likely to be your issue today.

I did notice that the slv_reg0-slv_reg3 registers within your core are set, but never read.  Instead, your code reads values output_1-output_4 from these addresses.  This could easily be the reason a self-test of register 0 would fail.

Dan

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Re: AXI4 Peripheral Lite slave Selftest error

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@dgisselq 

Thanks for your reply!

That is indeed true. I require full duplex communication between MB and VHDL. Is this a proper method or should I use a signal to load the slv_regx into the output_x and then output_x into the reg_data_out? This would give meaning to slv_reg0-3 again.

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Re: AXI4 Peripheral Lite slave Selftest error

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@jawkover,

I don't see a problem with it myself.  AXI requires that all outputs be need registered, and your core is doing that.  See S_AXI_RDATA signal for example.  I might clean the core up a touch and get rid of the slv_regs you aren't using, perhaps even adjust the self-test so that it passes, but other than that it looks fine to me.

Dan

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Re: AXI4 Peripheral Lite slave Selftest error

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@dgisselq 

True, but the problem is that the selftest writes to all the registers and then reads from them. If the written and read values are the same, then the AXI4 peripheral is working correctly. With the selftest failing and my program not working properly, I fear that something went wrong with the AXI4 periph.

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Re: AXI4 Peripheral Lite slave Selftest error

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Furthermore, I find this warning a bit worrysome:

WARNING: [Synth 8-6014] Unused sequential element loc_addr_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:236]

loc_addr is the key for the switch case:

	process (output_1, output_2, output_3, output_4, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
	begin
	    -- Address decoding for reading registers
	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
	    case loc_addr is
	      when b"000" =>
	        reg_data_out <= output_1;
	      when b"001" =>
	        reg_data_out <= output_2;
	      when b"010" =>
	        reg_data_out <= output_3;
	      when b"011" =>
	        reg_data_out <= output_4;
	      when b"100" =>
	        reg_data_out <= slv_reg4;
	      when b"101" =>
	        reg_data_out <= slv_reg5;
	      when b"110" =>
	        reg_data_out <= slv_reg6;
	      when b"111" =>
	        reg_data_out <= slv_reg7;
	      when others =>
	        reg_data_out  <= (others => '0');
	    end case;
	end process; 

If it indeed means that the register of the key to that switch case is removed then it could explain why the registers aren't accessible anymore. If I read that write, that is.

 

Jonathan

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Re: AXI4 Peripheral Lite slave Selftest error

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Yeah, that looks ominous.  I'm guessing that the warning is a nothingburger, just there to let you know that loc_addr is used internally within that process and never elsewhere, so it can be successfully optimized away (once your logic is implemented).

Dan

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Re: AXI4 Peripheral Lite slave Selftest error

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I rebuilt the entire peripheral, seperated the incoming and outgoing channels per slave and that works. S00 handles incoming data and S01 processes outgoing data, why this works and the combined slave does not, I haven't got a clue.

Perhaps the logic in vivado 2017.4.1's synthesizer doesn't support this method as it optimises the important signals out of the peripheral.

All I know is that it is very difficult to utilise MicroBlaze if there isn't a connection between it and surrounding VHDL components.The lack of proper tutorials or guides sadly doesn't help much either. Yes, there is the AXI reference manual, but I have scrolled through it and it is a very broad explanation of what an AXI peripheral can be. Perhaps the VHDL components would be better off inside the peripheral, but that would still mean that they signals require a connection to the AXI registers.

My solution holds at the moment, so this topic can be closed.

I want to thank you for your support @dgisselq, I very much appreciate it!

I hope that someone, perhaps an expert in AXI modules, could create an official bridge or explain how to create one that is stable and meant to be used. I somehow have the feeling that I am exploiting the AXI peripheral system a bit right now haha.

 

Jonathan

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Re: AXI4 Peripheral Lite slave Selftest error

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@jawkover,

I understand your concerns completely.

I don't work for Xilinx, neither have I ever used MicroBlaze.  (I've been known for using the open source ZipCPU instead, with AutoFPGA has a system integrator.)  However, I have been critical of Xilinx for picking such a complicated bus to interface with.

Perhaps the best evidence that the AXI bus is difficult to work with is the fact that Xilinx's own demonstration cores don't necessarily follow the bus standard.  You can read my evaluation of their AXI-lite slave core here.  I have yet to post my evaluation of their AXI (full) slave core, but I've now counted several bugs within it as well.  I'm currently holding off on posting this evaluation to hear if Xilinx has any interest in it.  So far, all I've heard has been crickets.

I've already posted my own tutorial of how to write an AXI-lite slave that (works, and) achieves twice the performance of Xilinx's demonstration slave.  You can find a copy of my own AXI-lite slave here, and even the (broken) Xilinx slave I examined here.  A more recent post presents the most common problems I've seen in AXI code.

I hope that someone, perhaps an expert in AXI modules, could create an official bridge or explain how to create one that is stable and meant to be used.

While it's not official, I have created an AXI-lite to WB bridge that has been formally verified.  It's also been used successfully on an FPGA, and there's even a VHDL wrapper for it.  Feel free to check it out and see if it's useful to you at all.  I personally find WB interface much easier to use.

Dan

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