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Explorer
Explorer
1,976 Views
Registered: ‎03-22-2016

AXI4 Stream Broadcaster width incorrect?

In Block Design of Vivado 2017.1, I add a block for "AXI4 Stream Broadcaster". By default the input stream port has a TDATA width of 8, the two output ports each have a width of 16. I would have expected them to be the same.

 

When I manually specify TDATA width for SI and MI to be 1, the slave TDATA width is properly set to 8, but the master TDATA width remains at 16. It seems that the master TDATA width is always exactly twice what I set it to be. As such, "auto" doesn't work, because it's doubling the stream width from the input to the output.

 

Am I misunderstanding how this block is supposed to work? I'm relatively new to design, but I can't find anything to indicate that the input and output should be anything other than equal widths, unless manually specified.

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Observer
Observer
1,649 Views
Registered: ‎02-12-2017

I encounter the same issue with AXI4_Stream_Broadcaster, looks like it's an old issue that xilinx didin't fix.

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/problem-with-TDATA-widths-in-AXI4-Stream-Broadcaster/td-p/499092

But I see someone successfully use this IP in his project, so there must be a way to fix it manually.

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Xilinx Employee
Xilinx Employee
237 Views
Registered: ‎02-05-2008

It looks like this is just an issue with the symbol creation in IPI, and not an actual functional problem.  Although the pin break-out on the symbol shows a width twice what it should be, if you click on the symbol pin and look at it’s properties, you should see the correct value for the CONFIG.TDATA_NUM_BYTES property.  The same thing applies to the TREADY and TVALID pins.

So ignore the vector widths that are shown on the symbol Mx interfaces, they do not reflect the actual AXI interface parameterization.  There is no easy way to edit this display problem.

It does look like this issue has been around for quite a while.  It is still evident in 2019.2.

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