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legendbb
Voyager
Voyager
1,311 Views
Registered: ‎07-28-2008

AXI4-Stream Data FIFO (1.1) slave.tready throttles after 63-clk.

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(Vivado 2018.2) single clock 240MHz or 156.25MHz, FIFO Depth is big: 8192, packet mode or not, Asynchronous Clocks = No.

I have a FIFO with the same settings in different location of my block design, its Tready doesn't seem to throttle at all. I capture by ILA, certain at the beginning of the data stream, the throttle throttles after 40something samples through.

Not sure how to troubleshoot this, maybe I'll shall tap on:

axis_data_count, axis_wr_data_count, and axis_rd_data_count ports.

Need to minimize throttling to maximize throughput. Especially don't understand what could cause the throttling.

tx_fifo_chocking.PNG

Please comment.

 

ps. still struggling with this, tried different clocking strategy. With slower clock the throttling seems happen at different fifo, does this suggest it might be timing related (I do have some small timing violation cross clock domain, but not Intra)? I don't have overflow while everything is on the same clock domain with deep fifo. I might have to test my own axis_data_fifo while waiting for comments.

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jg_bds
Scholar
Scholar
1,228 Views
Registered: ‎02-01-2013

 

You seem to be looking at this problem the wrong way.

TREADY of a M_AXIS interface is an input. Your problem is that the other end of the interface is throttling the data stream (supposedly because it's unable to accept more data at the moment), not at the FIFO end.

-Joe G.

 

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jg_bds
Scholar
Scholar
1,229 Views
Registered: ‎02-01-2013

 

You seem to be looking at this problem the wrong way.

TREADY of a M_AXIS interface is an input. Your problem is that the other end of the interface is throttling the data stream (supposedly because it's unable to accept more data at the moment), not at the FIFO end.

-Joe G.

 

View solution in original post

legendbb
Voyager
Voyager
1,216 Views
Registered: ‎07-28-2008
Thanks for attention. Sorry for being confusing, the ILA capture attached in my original post is the M_AXIS going into FIFO. (for some reason, ILA name doesn't match my actual net name)
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legendbb
Voyager
Voyager
1,199 Views
Registered: ‎07-28-2008
Shame on me, I got confused. Indeed the throttling is happening on the master port, and it's due to following axis_interconnect.
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