02-14-2019 04:53 PM - edited 02-16-2019 08:51 AM
(Vivado 2018.2) single clock 240MHz or 156.25MHz, FIFO Depth is big: 8192, packet mode or not, Asynchronous Clocks = No.
I have a FIFO with the same settings in different location of my block design, its Tready doesn't seem to throttle at all. I capture by ILA, certain at the beginning of the data stream, the throttle throttles after 40something samples through.
Not sure how to troubleshoot this, maybe I'll shall tap on:
axis_data_count, axis_wr_data_count, and axis_rd_data_count ports.
Need to minimize throttling to maximize throughput. Especially don't understand what could cause the throttling.
Please comment.
ps. still struggling with this, tried different clocking strategy. With slower clock the throttling seems happen at different fifo, does this suggest it might be timing related (I do have some small timing violation cross clock domain, but not Intra)? I don't have overflow while everything is on the same clock domain with deep fifo. I might have to test my own axis_data_fifo while waiting for comments.
02-18-2019 03:41 PM
You seem to be looking at this problem the wrong way.
TREADY of a M_AXIS interface is an input. Your problem is that the other end of the interface is throttling the data stream (supposedly because it's unable to accept more data at the moment), not at the FIFO end.
-Joe G.
02-18-2019 03:41 PM
You seem to be looking at this problem the wrong way.
TREADY of a M_AXIS interface is an input. Your problem is that the other end of the interface is throttling the data stream (supposedly because it's unable to accept more data at the moment), not at the FIFO end.
-Joe G.
02-18-2019 06:41 PM
02-19-2019 11:19 AM