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jargendas
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Registered: ‎04-02-2019

AXI4-Stream Data FIFO packet mode not working

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Hi everyone,

I'm using the AXI4-Stream Data FIFO (v2.0) from the AXI infrastructure package to buffer a data stream until the whole packet is ready. For this of course, I have to use packet mode.

As I understand, the expected behaviour is that the FIFO shows nothing on it's output until a TLAST is received. Unfortunately, that is not what is happening as can be seen in the picture. The data is written to the internal BRAM and the first word seems to be available on the TDATA-line of the master, but tvalid is never asserted.

fifo_problem.png

I did two further experiments:

- When packet mode is disabled, the FIFO behaves as expected (but does of course not wait for the TLAST)

- When the FIFO becomes full, TLAST does get asserted with packet mode enabled, as expected

Am I doing something wrong or is this just a bug in the core? If so, is there a fix/workaround?

Thank you,

Jargendas

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demarco
Xilinx Employee
Xilinx Employee
2,623 Views
Registered: ‎10-04-2016

Hi @jargendas ,

Yes, the M_AXIS side of the AXI4-Stream Data FIFO should assert TVALID within a few clocks of receiving TLAST on the S_AXIS side. The time can vary a bit depending on whether you are using synchronous or asynchronous clocking.

I ran a quick simulation and saw the expected behavior regardless of when the endpoint stream slave asserted TREADY. I also tried both synchronous and asynchronous clocking cases. 

Are you running your tests in simulation or hardware? Are you seeing any critical warnings?

Another thing to check is whether you are asserting resetn to the FIFO long enough. Most IPs require a minimum reset of 16 clocks. Failure to do this causes a lot of weird behavior in simulation.

Regards,

Deanna

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demarco
Xilinx Employee
Xilinx Employee
2,670 Views
Registered: ‎10-04-2016

Hi @jargendas ,

If TVALID isn't asserted, an AXI transaction is not in flight, so the TDATA bits are essentially don't cares.

You can find more details about the FIFO behavior for the AXI4-Stream Data FIFO v2.0 in the FIFO Generator Product Guide (PG057). Specifically, all AXI FIFOs operate in first-word fall-through mode. It provides the ability to look ahead to the next word available from the FIFO without issuing a read operation.

https://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v13_2/pg057-fifo-generator.pdf

Regards,

Deanna

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jargendas
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Registered: ‎04-02-2019

Hi @demarco ,

thank you for the answer, sadly I do not quite understand it. As seen in the image, S_AXIS_tvalid is asserted when transmitting data and the data is correctly written to the FIFO memory. However, the FIFO never asserts M_AXIS_tvalid somehow, which should be the case after receiving a TLAST to my understanding.

Maybe M_AXIS_tready has to be asserted first? But this would then not be compliant to the AXIS-standard, as a master is not allowed to wait for a tready first if I am not mistaken.

Looking forward to an answer,

Jargendas

 

Edit: To be clear, this is not about the FIFO generator, but about the AXIS data FIFO as described above.

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demarco
Xilinx Employee
Xilinx Employee
2,624 Views
Registered: ‎10-04-2016

Hi @jargendas ,

Yes, the M_AXIS side of the AXI4-Stream Data FIFO should assert TVALID within a few clocks of receiving TLAST on the S_AXIS side. The time can vary a bit depending on whether you are using synchronous or asynchronous clocking.

I ran a quick simulation and saw the expected behavior regardless of when the endpoint stream slave asserted TREADY. I also tried both synchronous and asynchronous clocking cases. 

Are you running your tests in simulation or hardware? Are you seeing any critical warnings?

Another thing to check is whether you are asserting resetn to the FIFO long enough. Most IPs require a minimum reset of 16 clocks. Failure to do this causes a lot of weird behavior in simulation.

Regards,

Deanna

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jargendas
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Registered: ‎04-02-2019

Hi @demarco,

I only held the reset pulse for 10 clocks, after extending it to 20 clocks it works.

Thank you very much for your help!

Jargendas

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