AXI4-Stream Interface RFSoC

[vapham]

Hello everyone,

I saw that in PG269 the AXI4-Stream Interface in which the number of AXI4-stream and the width of each bus depends on the bandwidth required by the mode of operation. But I am still confuse about this problem:

Single RF-DAC Input - 32 bits

As we can see in this figure, at 2 ns (~500 MHz) we have 2 samples Q0 and I0, therefore we have just only 1 GSPS (instead of 4 GPSP in the figure). May be I don't understand something!

Also, I don't know why we have s00_asix_tdata = 32 bits! 

Can you please explain for me.

Thanks with best regards

[johnmcd · Accepted solution]

For real data, one sample is 16bits.

But for I/Q data, one sample includes both I and Q. So one sample is 32bits.

And the RFDC can be configured for different data widths.

So for example:

If dwidth=32bits, (8x interpolation), 4Gsps, then the axis clk has to be 500MHz.

If you change RFDC dac axis to 64bits, then you could reduce clk to 250MHz.

[vapham]

Thanks @johnmcd  for your correct answer,

But I am still confuse about this figure as well as the figure 79 of PG269 V2.1. 

According to the document: 

PLdatarate = (DACdatarate * IQMode) / InterpolationRate = 4000*2/8 = 1000 MHz

PLFclock* PLnumword = PLDatarate

=> PLFclock = PLDatarate/PLnumword = 1000/1 = 1000 MHz

Where IQmode = 2 if I/Q data and  =1 if Real Data

So the 1000 MHz must be correct result

I verified with Figure 79 by using DC Tool in Vivado and I got the same result like above equation.

Please tell me where I am wrong

Thank you