06-12-2017 05:34 PM
I've encountered something odd trying to control some axi-streams in my block diagram... IP's with multiple slaves or masters seem to think they only have 1.
The setup for this particular piece is two axis data fifos, from each of which I want to extract a slice of tdata and merge the results into a single axis. I'm using an axis_combiner IP for this purpose. I connect the two output streams from the fifos to the respective inputs of the combiner, and then go to manually override the tdata signals for each by wiring in the aforementioned slices. Here's where it gets weird...I can override the individual bus signals for S00_AXIS, the override signals for S01_AXIS will not allow any connections on the diagram. If I try to draw a connection from S01's tready, for example, the connection instead extends from S00's tready, or it doesn't allow me to draw a connection at all. The TCL I see when I manually connect S00's tdata signal is
connect_bd_net [get_bd_pins axis_combiner_0/s_axis_tdata] [get_bd_pins xlslice_0/Dout]
Notice the net is simply "s_axis_tdata" not "S01_axis_tdata" or some such thing as you'd expect... it's as if the ip block thinks it only has one slave port.
To add to this confusion, there is a similar piece of the diagram where the reverse happens - a stream is split with an axis_broadcaster. I see this same exact behavior if I try to override the connections to M01 on the broadcaster. I hadn't noticed this before because I was always using the stream "as-is" rather than trying to override any signals, which seems to function properly.
I've tried deleting and re-instantiating the ip, changing the number of ports, closing and re-opening the design, closing and re-opening vivado, rebooting the VM I'm working in......this seems to persist. Searched for existing threads on this, but found nothing. Anybody seen this? I'm running Vivado 2016.2_AR67729 on Ubuntu 14.04. Thanks in advance for any tips
07-04-2017 07:42 PM
I saw this as well, in 2016.x versions. It does appear as though the interface connection stuff only sees one port where there should be several.
I don't use that in my design any more though so don't know if it still happens in 2017.x?