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Drake
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Registered: ‎04-22-2021

Access EMIO interface signals into the PL and "play" with them

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Hello,

I am using the following Zynq7000 SoC: XC7Z020-1CLG400I.

I know it is possible to route a PS signal (i.e. TTC0.Timer0 Wave-Out) through the EMIO interface to the PL.

My question is: Once the signal is on the EMIO interface, can I "play" with it inside the FPGA?

What I would like to do is the following:

- Route TTC0.Timer0 Wave-Out to the EMIO interface (programming properly the PS.SLCR registers)

- TTC0.Timer1 Wave-Out is already on the EMIO interface

- TTC0.Timer2 Wave-Out is already on the EMIO interface

- Pass the TTC0.Timer0/1/2 Wave-Out through a NOT block (programming properly the PL.FPGA)

- Route the 6 signal out of the PL (programming properly the PL.FPGA)

I've added a picture to figure it out.

Thank you!

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Drake
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Registered: ‎04-22-2021

Again thank you!

I think I got it.

I've attached a picture with my understanding.

Thanks!

View solution in original post

Cattura3.PNG
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derekm_
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Registered: ‎01-16-2019

What you want to do sounds perfectly normal. Note that you don't need to program the SLCR registers yourself though; you just need to enable the TTC(s) in the relevant tab in the Zynq block in IP integrator. Then you should be able to do whatever you want with the signals in the FPGA section.

enable_ttc.png

 

 

 

 

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Drake
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Registered: ‎04-22-2021

Hello drekm_,

thank you so much for your reply.

Googling around it seemed to me that the EMIO interface was just a way to extend the MIO interface and then that the signals on the EMIO interface were not really available at the FPGA, but they were just more PS inputs/output passing through the PL.

Anyway, my question is: How do I know on which pin of the FPGA the TTC0.Timer0/1/2 Wave-Out signals will be mapped?

Thanks!

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derekm_
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Registered: ‎01-16-2019

Once you're working in the programmable logic domain, it's up to you how you want to connect the pins to the top-level using XDC constraints. The options you have on the board you are using are also important, of course. For example, I have a simple circuit where I just connect all the TTC signals to PMOD JC of a Digilent Zybo-Z7-20 platform. The block diagram looks like the following:

make_external.png

 

And the pin locations are set in the XDC file as follows (the "#" are comments):

 

#========================================================#
# === TTC0/1 => PMOD JC ===
#========================================================#
set_property IOSTANDARD LVCMOS33 [get_ports TTC0_WAVE0_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports TTC0_WAVE1_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports TTC0_WAVE2_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports TTC1_WAVE0_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports TTC1_WAVE1_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports TTC1_WAVE2_OUT]

# TTC0_WAVE0 => PIN 1 = V15
# TTC0_WAVE1 => PIN 2 = W15
# TTC0_WAVE2 => PIN 3 = T11
# TTC1_WAVE0 => PIN 7 = W14
# TTC1_WAVE1 => PIN 8 = Y14
# TTC1_WAVE2 => PIN 9 = T12
set_property PACKAGE_PIN V15 [get_ports TTC0_WAVE0_OUT]
set_property PACKAGE_PIN W15 [get_ports TTC0_WAVE1_OUT]
set_property PACKAGE_PIN T11 [get_ports TTC0_WAVE2_OUT]
# PIN 4 (T10) NOT USED
set_property PACKAGE_PIN W14 [get_ports TTC1_WAVE0_OUT]
set_property PACKAGE_PIN Y14 [get_ports TTC1_WAVE1_OUT]
set_property PACKAGE_PIN T12 [get_ports TTC1_WAVE2_OUT]
# PIN 10 (U12) NOT USED

 

 

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Drake
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Registered: ‎04-22-2021

Thanks again derekm_!

Basically, I don't need to know on which FPGA input pin the TTC0.Timer0/1/2 Wave-Out PS signals will be mapped, because to manipulate them inside - let's say - my VHDL code, I can just use their simbolic name (TTC0_WAVE0/1/2_OUT) and the FPGA "knows" the pins where to get them.

Once I have manipulated them I need to specify, via XDC constraints, the output pins where the manipulated signals will be available.

Do you think I got it?

Thanks!

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derekm_
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Registered: ‎01-16-2019

I'm not really sure about the approach you are trying. To create Zynq-7000 designs, you do everything in IP Integrator. Even if you develop your own VHDL code to use with the Zynq, you need to convert your code to an IP module which is then also connected up in IP Integrator. UG1118 shows how to package up your code.

To elaborate, in your custom code, you can have (for example) 6 inputs for the TTC signals that you get via EMIO from the Zynq. You create your custom IP block and add it to the block diagram. Then you connect the TTC EMIO signals from the Zynq to the input signals on your block.

The outputs are just mapped to FPGA pins as normal, using XDC constraints. It is up to you where you want to route the signals, but it also depends on the options you have on your board.

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bruce_karaffa
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Registered: ‎06-21-2017

Almost true.  You can, but do not need to go through IP integrator.  You can just drop an RTL module into the block diagram.

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Drake
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Registered: ‎04-22-2021

Again thank you!

I think I got it.

I've attached a picture with my understanding.

Thanks!

View solution in original post

Cattura3.PNG
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derekm_
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Registered: ‎01-16-2019

Yes, that's almost the idea. The Programmable Logic and FPGA are effectively the same entity though.

Also, if you don't want to use custom logic, you can just add NOT gates to the IP Integrator canvas, in the form of Utility Vector Logic. That would be a much quicker way to do what you want. But generating a custom VHDL block is also a good way to learn, although it can be a bit painful to get right the first time.

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derekm_
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Registered: ‎01-16-2019

@bruce_karaffa, I am confused... do you mean drop a Zynq-7000 RTL module into the block diagram? And, isn't the the block diagram a fundamental part of IP Integrator? I know you can generate everything using TCL commands, but you still end up with a block diagram, right?

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bruce_karaffa
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Registered: ‎06-21-2017

@derekm_ I meant to point out that you do not need to IP Package an RTL module in order to drop it into a block diagram.  You may need to synthesize the RTL first.  I don't remember the details and I'm on the wrong computer to check, but I have about 5 working designs where the top level RTL is just an RTL module and not "packaged IP".  I don't think the block diagram editor or Vivado in general treats an RTL module any differently than RTL packaged as IP.

derekm_
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Registered: ‎01-16-2019

@bruce_karaffa, I see, thanks. Yes, that makes sense.

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Drake
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Registered: ‎04-22-2021

Thank you derekm_!

I will try it!

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Drake
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Registered: ‎04-22-2021

Thanks for the contribution bruce_karaffa!

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