05-02-2018 01:48 AM
I have a Zynq020 device, and have come from a VHDL background. Quite used to creating code to exercise LED displays. However the Zynq and Vivaldo is a totally different bread, all all in nice block diagrams.
I have code in the PL, this generates data packets of around 8x64 bits, that need to be written to a DDR address that the PL chooses. This address can be quite random, although it will be on a 64 bit boundary.
The HP0 access seems like the ideal way, and almost toying with the idea of monitoring AXI waveforms and writing the code myself. I have been reading loads of articles on accessing DDR from the PL, but it seems to be the address selection is the problem. Could create DMA from block ram to DDR, but how is the destination address set?
Currently I have block RAM that PL writes to and the PS takes that to write to DDR, but with to eliminate the processor.
I started to look into creating a custom peripheral, but it has no interface I could use from PL, just M_AXI and S_AXI, so thats probably not the direction to go.
Does anyone know where I can either find info on interfacing PL with HP0 directly, or by using a AXI block to take in the address, and data payload to drop into a place in DDR. I not knoly need to write, once all the writes are done, data processing is required to that will be done in PL(its currently in Zynq processor code), so will need to also read randomly.
05-02-2018 05:05 AM
Just found some interesting info on axi cdma.
So it has registers where source and destination address is set (didn't know this before).
Well I can make my source the block RAM. Looks like these registers can be programmed direct from RTL. The DMA should be able to directly copy from block ram to DDR.
I will give this ago later on.
05-05-2018 02:54 AM
You have several options, some of which depend on the required performance.
Are the data packets anything like a stream of packets? Then AXI-Stream could be a good choice. You can add an AXI-Fifo to your design to read or write them. For higher performance you can also choose AXI-DMA which automatically places the packets in DDR RAM.
You can also implement an AXI or AXI-Lite master in PL and write to DDR RAM yourself. This can give you real random access to the RAM.
In order of complexity: AXI-Stream is easiest, AXI-Lite is not too difficult, AXI4 is already complex and AXI4 with multiple overlapping bursts is hardest.
05-07-2018 11:48 AM
Thanks for the response..
The data is 8 lots of 64 bits to be written in a block, sequentially. These blocks can be at various locations. Looking into the AXI interface its not a difficult as it first appeared. I'm currently writing a block that interfaces with the AXI direct to HP0 (64bit @ 150mhz) of the Zynq.
It wont fully appreciate all AXI signals, but it will write single write and burst writes. I'll post it here once done, as it may be useful for someone else on a similar journey as me.
05-09-2018 01:48 AM
The solution is working. I have created RTL that is set off from GPIO, this runs through a state machine putting signals on the AXI HP0 interface. A burst of 8 lots of 64 bit writes happen to DDR ram location 0x10000000.
There are two parts to the state machine to write two different lots of data, exercised by two bits in GPIO. This is just to vary the data, so you can see a change when peeking into the RAM from the SDK.
The RTL is attached.
The GPIO is at address 0x41200000, writing to the high lighted box can start the statemachine, Writing 1, initializes mode 1 of the state machine, then write a zero sets it off.
So write a 1, then write a 0
A burst write will happen at address DDR 0x10000000
Writing 2 and then a 0 you get
The burst waveform sampled through putting a debug on AXI_HP0
Similar capture just zoomed out a bit.
Hope this can help someone else out, its been a good learning journey for me. I was originally a little scared of looking into how AXI works, and how much time it would take. It is actually not that bad using AXI, quite logical, and lots of info out there. I actually found an app note on AXI in Actel parts which helped me, AXI seems to be commonly used across many vendors. So lots of help out there.
My project file is 145Mb compressed. I'll find a place to store it, so people can download it, if they desire.
05-09-2018 03:35 AM
You made a classical error for AXI interfaces: a master MAY NOT wait for the slave to become Ready.
In state 0 you should just set awaddr, awlen and awvalid. Then wait for awvalid and awready to be '1' at the same time and then immediately set awvalid to '0'. So remove the if in state 0 and in state 1 add M00_AXI_awvalid<='0'.
In state 9 you should wait for M00_AXI_wready='1' once more before removing wvalid, wstrb and wlast.
And you also must keep bready until you see bvalid. I would set bready to '1' when transitioning to state 9.
Further, you're obliged to finish a burst to the end. So move your i2_start checks into state 20.
Btw. your indentation is quite awful.
05-11-2018 02:42 AM