12-10-2018 04:46 AM
We want to add 16 custom UART IP blocks to a ZCU102 Zync Ultrascale MPSoC design.
The UARTs work with interrupts, and will be managed by a custom Linux kernel driver that we will write.
The first problem is that according to the Zync Ultrascale TRM there are only 16 PL IRQ signals (from PL to GICs), thus our design will consume all available IRQ signals, with nothing to spare.
The second problem is that we believe that using 16 IP blocks will consume a large amount of FPGA resources (because each of these IP blocks needs an AXI interface).
What are the best options to solve these problem?
We are currently considering building an aggregate IP block which will combine several UART blocks into a single one. The aggregate IP block will contain an interrupt status register which will be a logical OR of the interrupt lines from all UART IPs. Interrupts will be level triggered.
12-11-2018 09:22 AM
Do you require a special custom UART? Or will the Xilinx IP uartlite or axi16550 do as well?
For both these IP's there are existing linux drivers. And AFAIK they can be used with a wired-OR interrupt (Utility Reduced Logic IP). Another option is to insert an extra INTC interrupt controller IP block.
I believe that 16 AXI-interfaces is not a massive burden for the PL either.
12-19-2018 02:09 AM
If using uartlite IP, and AXI INTC, are any changes needed in the linux driver or elsewhere, or will it work “out of box”?
Can you provide details what needs to be changed for the design to work with a AXI INTC?
12-19-2018 06:30 AM
The use of an AXI INTC and multiple UARTLITEs requires no modification of the linux kernel driver.
You do need to describe the UARTLITEs and INTC in the device tree of course. When using Petalinux this is done automatically.
And their kernel drivers must be enabled of course.
The wired-OR solution is described on the Uartlite Wiki.
The INTC solution would look something like this: