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Observer
Observer
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Registered: ‎06-07-2019

Address segments are inferred incorrectly

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I have a Microblaze core connected to an AXI Smartconnect, which connects to various slave peripherals. I have successfully added Uartlite, DMA, and interrupt controller peripherals, and now I want a second DMA (axi_dma_1) and an ethernet subsystem (axi_ethernet_0). However, after connecting them, I get a warning during validation: 

[BD 41-1629] </axi_ethernet_0/s_axi/Reg0> is excluded from all addressable master spaces.
[BD 41-1629] </axi_dma_1/S_AXI_LITE/Reg> is excluded from all addressable master spaces.

When I open up the Address Editor, I can see that the segments for the dma_1 and ethernet_0 are not mapped (first image). They are, however, mapped (and excluded) from dma_1's addresses (second image). So the problem seems to be that AXI SmartConnect is trying to connect DMA_1 (MM2S AXI Master) to Ethernet (AXI Slave) and DMA_1 (MM2S AXI Master) to DMA_1 (AXI Slave), instead of Microblaze (AXI_DP Master) to Ethernet (AXI Slave) and  (AXI_DP Master) to DMA_1 (AXI Slave). Does anyone know how to change the inner interconnect of the SmartConnect IP to route masters to the correct slaves?

 

addresssegments.PNG

 

addressexcluded.PNGsystemBD.PNG

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Address segments are inferred incorrectly

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Hi @cdv16 

My recommendation would be to use 2 different AXI smartconnect. One for the control of the IP (i.e. AXI4-Lite interface) and one for the memory access.

This should help the automation tool and clean the design.

If you only want to fix, you can right click on the IP under "Excluded Address Segements" and re include the segments.

Let me know if you have any question about this,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
422 Views
Registered: ‎11-09-2015

Re: Address segments are inferred incorrectly

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Hi @cdv16 

My recommendation would be to use 2 different AXI smartconnect. One for the control of the IP (i.e. AXI4-Lite interface) and one for the memory access.

This should help the automation tool and clean the design.

If you only want to fix, you can right click on the IP under "Excluded Address Segements" and re include the segments.

Let me know if you have any question about this,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Observer
Observer
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Registered: ‎06-07-2019

Re: Address segments are inferred incorrectly

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@florentw, that makes a lot of sense, thanks. 

 

Now I have two AXI smartconnects. I connected Microblaze's AXI_DP master interface to one smartconnect, and both AXI_DC and AXI_IC (as well as the DMA's master interfaces which need access to DDR3, such as M_AXI_SG) to the other smartconnect. Then I routed the AXI_DP smartconnect to all the peripherals' S_AXI interface, and the other smartconnect I routed only to the DDR3 memory controller's S_AXI interface. It makes perfect sense to have peripheral transactions on one network, and memory transactions on another. 

 

However, when I looked at the address editor, all the peripherals were addressable by microblaze Data address space EXCEPT the IIC peripheral. So I placed the IIC S_AXI interface on the other smartconnect, thinking that instead of being accessed by Microblaze's AXI_DP, it must be accessed by AXI_DC or AXI_IC. After this change, the IIC address segment appeared in Micoblaze Data and Instruction address spaces. 

 

Was this swap the right thing to do? Why would a peripheral's S_AXI not be talked to by Microblaze's DP (Data Peripheral) interface? 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Address segments are inferred incorrectly

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Hi @cdv16 

Yes I would expect the AXI IIC to be accessible for the MB AXI_DP. Do you see it in the excluded segment? Did you try to click again on re-validate?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer
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Registered: ‎06-07-2019

Re: Address segments are inferred incorrectly

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@florentw, I am not sure why I couldn't map in the IIC address segment to Data Peripheral address space. After trying it a second time, your solution worked. This is my final configuration that succeeded:

 

I have a couple of final questions:

 

The smartconnect on the right (routing to DDR3) was configured automatically with two clock inputs, but all AXI interfaces on all devices connected to this smartconnect use the same clock (ui_addn_clk_0). Why is this?

Also, why do Instruction and Data caches reside in DDR3 memory? I would think that BRAM is faster. After all, non-cached instructions and data are in DDR3. 

Thanks for your help!

 

smartconnects.PNG

 

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Registered: ‎11-09-2015

Re: Address segments are inferred incorrectly

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@cdv16 wrote:

@florentw, I am not sure why I couldn't map in the IIC address segment to Data Peripheral address space. After trying it a second time, your solution worked. This is my final configuration that succeeded:

 

I have a couple of final questions:

 

The smartconnect on the right (routing to DDR3) was configured automatically with two clock inputs, but all AXI interfaces on all devices connected to this smartconnect use the same clock (ui_addn_clk_0). Why is this?

[Florent] - I do not know, probably the automation tool didn't catch everything correctly. But note that there are also options when running the automation tools which create the smartconnect. You need to chck to make sure everything is selected properly

Also, why do Instruction and Data caches reside in DDR3 memory? I would think that BRAM is faster. After all, non-cached instructions and data are in DDR3. 

[Florent] - Same thing, this is just a settings. Yes it would be faster using BRAM and you should have the option in the automation tool. Just look on the window which pop-up after clicking run automation

Thanks for your help!

 

smartconnects.PNG

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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