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Charlycop
Observer
Observer
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Registered: ‎11-28-2020

Advantage of Multi slave AXI on my IP ?

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Hi,

This is for an academic project, and I don't have time to explore axi full burst for my IP, but in order to accelerate the transfers from the PS side to the PL side, I'm wondering if the PS can initiate several transfers on different axi lite slave "in the same time" ?

I have a big array of 1000+ 32 bits data to send from PS to PL, and I'm doing it one by one with an axi lite successfully (inside a for loop). (I'm planning to send 3 data of 9 bits (27 bits) in the same time too, but this is not my question).

What I mean by "in the same time" : will the PS has to wait the first transfer to finish on the slave1 in order to launch the next transfer on the slave2 ? if it doesn't need to wait, it will be an easy way to accelerate my transfer by adding several axi lite slave on my IP.

I'm using vivado 2018.3 on Windows 10 pro 20H2 with a surface pro 4, i7 CPU and 16Go or RAM.
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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@Charlycop ,

By default, the ARM will not issue multiple requests to the PL.  Each request of the PL must finish before it issues the next.

There are plenty of other limitations in the system following, such as the Xilinx interconnect limiting AXI-lite connections to one transfer at a time, or the poor implementation of Xilinx's AXI-lite demonstrator that only allows one write transaction every three clocks, but the problem ultimately starts at and rests in the PS's in ability to issue multiple requests of the PL at a time.

The solution to this problem is twofold.  First, you'll want to use an AXI DMA of some type.  Such a DMA will be able to transfer data at one beat per clock--the fastest the bus can go.  Second, you'll want to implement an AXI (full) interface to make the most use of this capability.  If you still want to maintain the simplicity of an AXI-lite interface, you might wish to consider a full speed AXI to AXI-lite bridge that won't slow your interface down together with a better AXI-lite example to start from.

Dan

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vanmierlo
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Registered: ‎06-10-2008

I don't think that this will give you any advantage. Transferring data using a for loop is not optimal either.

Maybe you should just try it out.

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@Charlycop ,

By default, the ARM will not issue multiple requests to the PL.  Each request of the PL must finish before it issues the next.

There are plenty of other limitations in the system following, such as the Xilinx interconnect limiting AXI-lite connections to one transfer at a time, or the poor implementation of Xilinx's AXI-lite demonstrator that only allows one write transaction every three clocks, but the problem ultimately starts at and rests in the PS's in ability to issue multiple requests of the PL at a time.

The solution to this problem is twofold.  First, you'll want to use an AXI DMA of some type.  Such a DMA will be able to transfer data at one beat per clock--the fastest the bus can go.  Second, you'll want to implement an AXI (full) interface to make the most use of this capability.  If you still want to maintain the simplicity of an AXI-lite interface, you might wish to consider a full speed AXI to AXI-lite bridge that won't slow your interface down together with a better AXI-lite example to start from.

Dan

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