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enterbruce
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Registered: ‎04-08-2019

As for Zynq UltraScale+ MPSoC, could PS-PL AXI interface(S_AXI_HPC*/HP*_FPD) access address range of M_AXI_HPM0/1_FPD ?

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Hi, As for Zynq UltraScale+ MPSoC, could PS-PL AXI interface(S_AXI_HPC*/HP*_FPD) access address range of M_AXI_HPM0/1_FPD ? If the data path exist, how to enable it? Your comments will be very appreciated. Sincerely Wendy
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demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @enterbruce ,

If you can hook up your PL master AXI interface directly to the S_AXI_HPC*/HP*_FPD port, the address range will get forwarded into the PS, decoded by the PS interconnect and forwarded to the M_AXI_HPM0/1_FPD.

This won't work if there is a soft interconnect between the PL master AXI and the S_AXI interface on the PS. In their default configurations, both AXI Interconnect and SmartConnect will issue a DECERR because the PS does not expose the M_AXI_HPM0/1_FPD address ranges in Address Editor. The soft interconnects derive their configuration from the ranges in Address Editor.

Do you need a soft interconnect in the path?

Regards,

Deanna

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demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @enterbruce ,

If you can hook up your PL master AXI interface directly to the S_AXI_HPC*/HP*_FPD port, the address range will get forwarded into the PS, decoded by the PS interconnect and forwarded to the M_AXI_HPM0/1_FPD.

This won't work if there is a soft interconnect between the PL master AXI and the S_AXI interface on the PS. In their default configurations, both AXI Interconnect and SmartConnect will issue a DECERR because the PS does not expose the M_AXI_HPM0/1_FPD address ranges in Address Editor. The soft interconnects derive their configuration from the ranges in Address Editor.

Do you need a soft interconnect in the path?

Regards,

Deanna

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enterbruce
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Registered: ‎04-08-2019

Hi,

Get it. Thanks.

Sincerely Wendy

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