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2,384 Views
Registered: ‎01-20-2014

Autogenetaion of pin constraints for the zynq design using Vivado

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hi.,

i am designing custom board using zynq-7z045-900i.

i did my basic design in vivado HLS.

i have systhesis it. 

can i able to generate the tool recommended pin constraints to my design.

this i want to do it and used the same pin assignments for my PCB design.

i didnt find anything about this auto generation of pins.

i m using ENET1 , SPI0,SPI1,IIC1 on EMIOs.

 

any guidelines much appriciated.......

thanks in advance.................

 

 

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2,936 Views
Registered: ‎01-20-2014

hi all.,

i came to know the auo placeing io ports.

after synthesis i went io pin planning(defalut layout). selected auto io pin placing of each interface .

....

BK.,

View solution in original post

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Highlighted
2,937 Views
Registered: ‎01-20-2014

hi all.,

i came to know the auo placeing io ports.

after synthesis i went io pin planning(defalut layout). selected auto io pin placing of each interface .

....

BK.,

View solution in original post

0 Kudos