07-31-2014 07:12 PM
I used the AXI EMC core to do some initial experimentation with the Nexys 4's PSRAM, but it was a little complicated to set up initially, and turned out to be very difficult to use the (poorly documented) page mode support that's supposedly part of that IP. So I decided to learn something about AXI and wrote my own. It handles the operations necessary to use the Micron PSRAM in page mode to optimize read-time and exposes it as a standard AXI4 slave and can be easily connected to a Vivado block diagram.
Since Digilent has yet to post any embedded system examples for the Nexys 4 in Vivado, I thought that others trying to cook one up might benefit from the experience, so I've packaged my IP and made it available via Github under the MIT Open Source license here: https://github.com/andrewsil1/NexysPsram. To use it, you would simply use Git to clone the repository, and point to that local directory copy as a user IP repository in the Vivado UI, then add the "psram" IP with the Add IP button as usual within your block diagram.
Details in the Readme follow:
This project contains the source code for an AXI4-compatible PSRAM controller, as implemented on the Digilent Nexys4 development board. I decided to create this project after doing some experimentation with Vivado's built-in "AXI EMC" IP. The EMC supports the PSRAM inasynchronous mode, but it's somewhat difficult to use it to program the PSRAM into page mode, and once it is, it's not particularly well optimized for that configuration, and some redundant reads are seen which waste cycles. So I decided to create my own from scratch, which is represented here and was an excellent learning experience to become familiar with the semantics of the AXI4 bus.
The core could probably be optimized to squeeze out a few more cycles of overhead here and there between consecutive operations, but it's been validated to run in a relatively reliable and stable fashion as it stands here. I hope you find good use for it and makes your Nexys4 projects simpler.
-- Andy Silverman, 7/31/2014
- Created from the Xilinx Vivado 2014.2 AXI IP creation sample, and derived from their original block RAM mplementation.
- The block RAM instantiation is replaced with original logic to call a new module of my own design to control the 16MB Micron PSRAM.
- The PSRAM runs in asynchronous page-read mode. Use of page-read allows consecutive reads to take place in significantly less time on nearby addresses (i.e. 20ns per 16 bits for addresses in the same 16-word "page", rather than 70ns.) Unfortunately, writes do not allow the same reduction in access time.
- The IP is optimized to recognize when memory accesses cross a page boundary and require a new 70ns access and CEN line toggle to continue valid operation. Similarly, the IP also recognizes when the CEN line has been low for a period of time approaching the Tcem limit of 4us documented in the datasheet and will automatically force CEN to cycle to permit memory refresh to operate normally without data corruption. Thus, operation with all the benefits of page-read mode is completely automatic without any intervention from the system designer.
- Compatible with AXI4 implementations where the AXI clock is 100Mhz and 32-bits wide. Changing to a different AXI clock speed would require revision of the PSRAM logic to comply with the asynchronous timing requirements.
- Unaligned and/or narrow reads (e.g. 16 bit or 8 bit memory access) are somewhat optimized to avoid unnecessary memory operations accessing the not-requested half of the 32 bit DWORD when possible.
- Supports basic FIXED, INCR, and WRAP bus transactions. Can be connected to Microblaze DC or IC cache interfaces for further performance enhancement.
- Validated to successfully pass all automatically generated Xilinx SDK memory tests with Microblaze caching of this memory region enabled and disabled. Some revisions to the sample's internal control logic were necessary because transactions to PSRAM do not complete in a single cycle as they do with block RAM.
- Compatible with AXI4 implementations where the AXI clock is 100Mhz and 32-bits wide. Changing to a different AXI clock speed would require revision of the PSRAM logic to comply with the asynchronous timing requirements. It also probably wouldn't be a huge amount of work to support a 64-bit wide AXI data bus, but it's not currently set up for that in all the places where it would need to be.
- Licensed under the terms of the included MIT License. I hope you find it useful.
09-09-2014 03:33 PM
This looks awesome and potentially usable with my project. I'm a bit new to memory interfacing, so my question is, once i import your module into my design, do I have to attach ports to any specific constraints in the .xdc for the nexys cellular RAM or is the RAM encapsulated within this design?