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yifeizhao
Visitor
Visitor
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Registered: ‎09-28-2018

Axi dma S2MM receive data lost 1st frame per BD cycle

Hi,

I am using Axi Dma in SG cyclic mode to transfer ADC data to PS and then transfer to ethernet.

I found a issue, which is the same as the post before.

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Axi-dma-S2MM-receive-data-are-not-all-perfectly-normal/m-p/1092069

Basically, when the Bd ring re-initialized, the 1st frame data will be lost due to DMA setup delay. Instead of the solution mentioned in previous post, is there any update right now to solve this problem? Thank you.

Yifei 

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abommera
Xilinx Employee
Xilinx Employee
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Registered: ‎10-12-2018

Hi @yifeizhao ,

You would need to use the cyclic mode without using multichannel mode.

abommera_0-1601984699913.png

 

Does AXI DMA report in any errors in status registers?

May I know the reason that you are looking for a solution other than in the forum post?

 

Thanks & Regards
Anil B
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yifeizhao
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Registered: ‎09-28-2018

There is no AXI DMA error reported. The DMA setup is shown below.

Capture.GIF

The PL setup is shown below. Basically, a counter sends data to AXI DATA FIFO and then read by AXI DMA. A packet generator is inserted in the middle for TLAST generation.

Capture2.GIF

The PS code is modified from "xaxidma_example_sgcyclic_intr.c" example. But only DMA S2MM is used to send counter data in SG cyclic mode.

My major concern is the words in AXI DMA datasheet (PG021) on throttling. It may allow the AXI DMA to read FIFO data before setting up. Is there any PL signal from AXI DMA to indicate AXI DMA is set up without throttling?

Capture3.GIF

 

 

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