10-06-2020 01:56 AM
I am using Axi Dma in SG cyclic mode to transfer ADC data to PS and then transfer to ethernet.
I found a issue, which is the same as the post before.
Basically, when the Bd ring re-initialized, the 1st frame data will be lost due to DMA setup delay. Instead of the solution mentioned in previous post, is there any update right now to solve this problem? Thank you.
10-06-2020 04:46 AM
Hi @yifeizhao ,
You would need to use the cyclic mode without using multichannel mode.
Does AXI DMA report in any errors in status registers?
May I know the reason that you are looking for a solution other than in the forum post?
10-06-2020 11:38 AM
There is no AXI DMA error reported. The DMA setup is shown below.
The PL setup is shown below. Basically, a counter sends data to AXI DATA FIFO and then read by AXI DMA. A packet generator is inserted in the middle for TLAST generation.
The PS code is modified from "xaxidma_example_sgcyclic_intr.c" example. But only DMA S2MM is used to send counter data in SG cyclic mode.
My major concern is the words in AXI DMA datasheet (PG021) on throttling. It may allow the AXI DMA to read FIFO data before setting up. Is there any PL signal from AXI DMA to indicate AXI DMA is set up without throttling?