07-23-2019 01:31 AM
Using Vivado 18.3.
I am currently trying to write data to an Axi-stream FIFO v4.2 (pg080) using the axi-stream interface.
I am deserialising and presenting a 32 bit wide word to the stream interface of the FIFO. I then assert tvalid and wait for tready before deasserting tvalid.
My understanding of the interface is that if both tready and tvalid are asserted on a clock edge whatever is on tdata is transferred on the axi-stream interface. Am I being obtuse? Is there something I'm missing?
I have simulated the design and I can see my deserialiser driving the axi-stream interface but I cannot see any evedence that the FIFO is clocking the data in. I've attached a snapshot of the interface during my simulation.
What am I missing?
07-23-2019 02:34 AM
For the sake of others who might be reading this, I'll note that this post has been sent to multiple sub forums.
This issue of clock edges really tripped someone up the other day in another forum thread, so let me try to clear it up. All transitions take place on clock edges. The new data is set based upon what was on the lines before the clock edge. While electrically things can change between clock edges, the tools help to make certain that all such changes settle by the time of the next clock edge. For this reason, your typical trace shows clock periods where data is constant.
I only say this because it is often simpler to discuss the data periods, rather than to get hung up over the edges. If it helps, you can imagine the positive edge of the clock takes place a small fraction of the clock period just before any change.
In your example below, there is a data period showing that both TREADY and TVALID are high for one clock period. During this clock period, a word of data was transferred as you have desired. The READY flag was held high, and the VALID flag was set high on the positive edge of a given clock period. On the positive edge following the clock period where READY and VALID were both high, the FIFO clocked in data.
This was the performance you wanted, right?
07-23-2019 02:56 AM
Well yes, that is my intention.
My question centres around whether or not I am driving this interface correctly.
Driven as in my simulation I do not see any data enter into the FIFO. Like I said, and like you seem to confirm, if data is on the bus while valid and ready are asserted for one cycle the data should be transferred into the FIFO.
I've taken two Axi-stream FIFOs (one tx only and one rx only) and connected back to back through the stream interface. I then sent data and all is well. My Linux kernal can write and read data using Axi-Lite to and from the FIFOs. I've then disconnected the Tx FIFO and inserted my deserialiser driving the interface as shown and now the receive FIFO does not seem to accept any data.
I'm a little stumped. Do I need to use TLast? I don't think I do. The FIFO stream interface doesn't have Tstrb either so I've not implemented that in my design.
07-23-2019 03:06 AM
Try formally verifying your design. I think you'll find the bug rather quickly. Indeed, I've now found a *lot* of bugs through that process--things that had passed simulation and so I had thought they were "working".
In this case, I'd look for bugs at both ends of the FIFO. My first guess would be that the AXI-lite controller was broken--since I've seen a lot of problems there.
07-23-2019 03:17 AM
AXI Stream is a really easy interface to verify. All you really need to verify is that the data doesn't change as long as the interface is stalled.
assert property (@(posedge ACLK) disable if (!ARESETN) (TVALID && !TREADY) |=> $stable(TDATA) && $stable(TLAST));
In this case, the interface isn't stalled, so you are driving the interface properly. Even more, you are sending a transaction through it--which was what you intended to do.
So ... I'd look elsewhere for the bug,
07-23-2019 03:44 AM
On page 37 of PG080 it states that tlast along with tvalid denotes the end of a packet in both modes during receive. I now assert tlast with each word and the data is now being written to the FIFO.