05-30-2017 02:39 AM
05-30-2017 03:05 AM
06-05-2017 11:38 AM
06-05-2017 10:57 PM
I think also Axi4-Stream Interconnect for true choice for switching the different clock speed Axi4-Stream interfaces.
But we could not make this IP operational, unfortunately, in our SW. How should I connect one Slave to one Master in SW ? I tried run only these lines in the document pg085-axi4stream-infrastructure.pdf, page 28. But switching is not working. And what is the #Commit registers here? I did not write any commit registers.
06-14-2017 05:07 AM
I try to learn how to work AXI4-Stream Switch IP when 'disabled use control register routing'.
The two routing options available are TDEST routing and control register routing. The TDEST based routing uses RTL parameters configured before synthesis to control the routing... is written in document pg085-axi4stream-infrastructure.pdf , page 16.
so what does it mean? Should I arrange TDEST signal in HDL file of IP. Should there be a TDEST signal all slaves interfaces, when disabled use control register routing ?