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johndeerepec
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Registered: ‎04-22-2009

BRAM from Microblaze and VHDL

I am looking for a Way to write a value from MicroBlaze to a Block RAM location, and then read that data from a custom VHDL module at that same location.  Any ideas?

 

Thanks!

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moharram2009
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Registered: ‎03-16-2009

if it is not important to use BRAM and the data is small, use xps_gpio core to stablish a connection between HW section and Processor Section. by this way the data sent & receive should be asynchronous thtough acknowledgement.

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johndeerepec
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Registered: ‎04-22-2009

Thanks, I will give that a try.  It may work for one of my applications, but the other probably will still need the BRAM due to amount of data.  I am also trying to free up logic on that one and would prefer to use the BRAM (have external memory for soft core).

 

Any other ideas?

 

Thanks!

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bassman59
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johndeerepec wrote:

I am looking for a Way to write a value from MicroBlaze to a Block RAM location, and then read that data from a custom VHDL module at that same location.  Any ideas?

 

Thanks!


Simple --make your peripheral core ('user_logic.vhdl') work with a single memory space. Implement the memory as a dual-port. Connect the PLB slave stuff to one side, connect your other logic to the other side, and there it is.

 

-a

----------------------------Yes, I do this for a living.
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johndeerepec
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Registered: ‎04-22-2009

That sounds like what I want to accomplish, the problem I am having is determining how to set the same BRAM for both the VHDL and the softcore.  Is there a constraint I can add?

 

Thanks.

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goran
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

When you add a bram_block in XPS it has two bram ports.

Connect one bram port to a xps_bram_if_cntlr and the other port to your own peripheral.

 

You can do the same thing with LMB but you would use lmb_bram_if_cntlr instead.

Depending on how data you will transfer, LMB can be a better choice.

LMB access has a latency of 1 or 2 clock cycles while PLB will more be 6-8 clock cycles.

 

Göran

 

goran
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

One other thing, the simplest way to send some signals value to your code is to use FSL.

It just becomes wires from MicroBlaze.

 

Göran

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bassman59
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Registered: ‎02-25-2008


johndeerepec wrote:

That sounds like what I want to accomplish, the problem I am having is determining how to set the same BRAM for both the VHDL and the softcore.  Is there a constraint I can add?

 

Thanks.


My VHDL infers the BRAM, and decodes the PLB slave address/chip-select/write-enable/byte-lane-enables as necessary.

 

-a

----------------------------Yes, I do this for a living.
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moharram2009
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Registered: ‎03-16-2009

plz

further description about using Custom IP Core ???

thnx

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mats_randgaard
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Registered: ‎05-25-2009


goran_bilski wrote:

When you add a bram_block in XPS it has two bram ports.

Connect one bram port to a xps_bram_if_cntlr and the other port to your own peripheral.

 

You can do the same thing with LMB but you would use lmb_bram_if_cntlr instead.

Depending on how data you will transfer, LMB can be a better choice.

LMB access has a latency of 1 or 2 clock cycles while PLB will more be 6-8 clock cycles.


My application sends some data from BRAM as UDP packets with lwIP (PBUF_REF). Do the EMAC communicate directly with the xps_bram_if_cntlr on the PLB bus or do all the data go through some other modules on their way from BRAM to EMAC?

 

My question is, when is LMB a better choice?

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mats_randgaard
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Registered: ‎05-25-2009


moharram2009 wrote:

further description about using Custom IP Core ???


 See the chapter called "Creating Your Own Intellectual Property (IP)" in "EDK Concepts, Tools, and Techniques."

 

Version 11: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/edk_ctt.pdf (chapter 7)

Version 10: http://www.xilinx.com/support/documentation/sw_manuals/edk10_ctt.pdf

Version  9: http://www.xilinx.com/support/documentation/sw_manuals/edk92i_ctt.pdf (chapter 5)

Message Edited by mats_randgaard on 06-10-2009 02:15 PM
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william.kafig
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Registered: ‎01-07-2009

I think that many of the folks that posted answers have done a good job and I'm only going to re-iterate what they said - but with some code...

 

Here's an instantiation of an embedded module from within a VHDL module. Note the access to the BRAM - just the address, data, enable, and clock (this was designed to read results produced by the processor, you would need to add write data and a write enable for full dual-port R/W support, but you get the idea...)

 

        --
        ------------------------------------------------------------------------------------------------------
        --
        -- ***** Microprocessor managemenet *****
        --
        -- Bug List: "Create New Source" allows illegal characters ('-') in the project name - mhs fails
        --
        ------------------------------------------------------------------------------------------------------
        --
        mb_subsystem: video_processor PORT MAP(               
                buffered_clock                     => clk100MHz,
                reset_n                                 => systemReset_n,
               
                rx                                     => rx,
                tx                                     => tx,       
               
                VSync_end                             => VGA_VSyncExited,
                VSync_start                         => VGA_VSyncEntered,
               
                BRAM_Dout_pin                         => VGA_data,
                BRAM_Addr_pin                         => VGA_address,
                BRAM_EN_pin                         => vcc(0),
                BRAM_Clk_pin                         => clk100MHz,
               
                pipeToProcessor_full             => open,
                pipeToProcessor_data             => FSL_dataTo,
                pipeToProcessor_writeEnable     => tenHzEnable,
                pipeToProcessor_clock             => clk6_25MHz,
               
                pipeFromProcessor_ready         => FSL_ready,
                pipeFromProcessor_data             => FSL_dataFrom,
                pipeFromProcessor_readEnable     => tenHzEnable,
                pipeFromProcessor_clock         => clk6_25MHz

            );    

 

From the microprocessor side, you need to make the BRAM dual-port ...

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = videoMemoryController
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x81810000
 PARAMETER C_HIGHADDR = 0x8181ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE PORTA = videoMemoryController_PORTA
END

BEGIN bram_block
 PARAMETER INSTANCE = videoMemory
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = videoMemoryController_PORTA
 PORT BRAM_Addr_B = BRAM_Addr
 PORT BRAM_EN_B = BRAM_EN
 PORT BRAM_Clk_B = BRAM_Clk
 PORT BRAM_Din_B = BRAM_Dout
END

 

 

... and bring the necessary lines "external".

 PORT BRAM_Addr_pin = BRAM_Addr, DIR = I, VEC = [0:31]
 PORT BRAM_EN_pin = BRAM_EN, DIR = I
 PORT BRAM_Clk_pin = BRAM_Clk, DIR = I, SIGIS = CLK
 PORT BRAM_Dout_pin = BRAM_Dout, DIR = O, VEC = [0:31]

 

This is taken from an example in the Advanced Techniques of EDK version 10.1

 

I hope this helps!

 

william.kafig
Xilinx Employee
Xilinx Employee
7,525 Views
Registered: ‎01-07-2009

I think that many of the folks that posted answers have done a good job and I'm only going to re-iterate what they said - but with some code...

 

Here's an instantiation of an embedded module from within a VHDL module. Note the access to the BRAM - just the address, data, enable, and clock (this was designed to read results produced by the processor, you would need to add write data and a write enable for full dual-port R/W support, but you get the idea...)

 

        --
        ------------------------------------------------------------------------------------------------------
        --
        -- ***** Microprocessor managemenet *****
        --
        -- Bug List: "Create New Source" allows illegal characters ('-') in the project name - mhs fails
        --
        ------------------------------------------------------------------------------------------------------
        --
        mb_subsystem: video_processor PORT MAP(               
                buffered_clock                     => clk100MHz,
                reset_n                                 => systemReset_n,
               
                rx                                     => rx,
                tx                                     => tx,       
               
                VSync_end                             => VGA_VSyncExited,
                VSync_start                         => VGA_VSyncEntered,
               
                BRAM_Dout_pin                         => VGA_data,
                BRAM_Addr_pin                         => VGA_address,
                BRAM_EN_pin                         => vcc(0),
                BRAM_Clk_pin                         => clk100MHz,
               
                pipeToProcessor_full             => open,
                pipeToProcessor_data             => FSL_dataTo,
                pipeToProcessor_writeEnable     => tenHzEnable,
                pipeToProcessor_clock             => clk6_25MHz,
               
                pipeFromProcessor_ready         => FSL_ready,
                pipeFromProcessor_data             => FSL_dataFrom,
                pipeFromProcessor_readEnable     => tenHzEnable,
                pipeFromProcessor_clock         => clk6_25MHz

            );    

 

From the microprocessor side, you need to make the BRAM dual-port ...

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = videoMemoryController
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x81810000
 PARAMETER C_HIGHADDR = 0x8181ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE PORTA = videoMemoryController_PORTA
END

BEGIN bram_block
 PARAMETER INSTANCE = videoMemory
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = videoMemoryController_PORTA
 PORT BRAM_Addr_B = BRAM_Addr
 PORT BRAM_EN_B = BRAM_EN
 PORT BRAM_Clk_B = BRAM_Clk
 PORT BRAM_Din_B = BRAM_Dout
END

 

 

... and bring the necessary lines "external".

 PORT BRAM_Addr_pin = BRAM_Addr, DIR = I, VEC = [0:31]
 PORT BRAM_EN_pin = BRAM_EN, DIR = I
 PORT BRAM_Clk_pin = BRAM_Clk, DIR = I, SIGIS = CLK
 PORT BRAM_Dout_pin = BRAM_Dout, DIR = O, VEC = [0:31]

 

This is taken from an example in the Advanced Techniques of EDK version 10.1

 

I hope this helps!

 

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jiangyuebing
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4,490 Views
Registered: ‎02-24-2009

Hi, :

  where is the pdf for "Advanced Techniques of EDK version 10.1" you have mentioned?

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