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qwerty1234578
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Registered: ‎05-01-2016

BRAM write access, MicroBlaze

Hi, guys.

I am newbie in FPGA and I need you help.

I am create microblaze core in XPS and add bram block and axi bram controller. Generate adresses, and have base bram adress as 0x41218000.

Then in SDK I am write 

 

XBram_WriteReg(0x41218000, 0, 0xEE);

but in 0x41218000 no EE, there 0000000. (i am see memory in Debug)

Then I am trying example from EDK folder, init structure looks like that:

1.png

 

 WriteAccess - zero.

 

Then I am look to file "xparameters.h" 

 

/* Definitions for peripheral AXI_SHARED_BRAM_CTRL_0 */
#define XPAR_AXI_SHARED_BRAM_CTRL_0_DEVICE_ID 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_DATA_WIDTH 32
#define XPAR_AXI_SHARED_BRAM_CTRL_0_ECC 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_FAULT_INJECT 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 1
#define XPAR_AXI_SHARED_BRAM_CTRL_0_WRITE_ACCESS 0
#define XPAR_AXI_SHARED_BRAM_CTRL_0_S_AXI_BASEADDR 0x41218000
#define XPAR_AXI_SHARED_BRAM_CTRL_0_S_AXI_HIGHADDR 0x41219FFF
#define XPAR_AXI_SHARED_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF 
#define XPAR_AXI_SHARED_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF 

/* Canonical definitions for peripheral AXI_SHARED_BRAM_CTRL_0 */
#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_SHARED_BRAM_CTRL_0_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_0_WRITE_ACCESS 0
#define XPAR_BRAM_0_BASEADDR 0x41218000
#define XPAR_BRAM_0_HIGHADDR 0x41219FFF

and defines ...write_accsess - zero.

 

#define XPAR_AXI_SHARED_BRAM_CTRL_0_WRITE_ACCESS 0
#define XPAR_BRAM_0_WRITE_ACCESS 0

 If i am manualy set them zero, they automaticaly reset to 0. Anyway, nothing works. Can you help me, plz?

Spartan6, XPS 14.7.

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htsvn
Xilinx Employee
Xilinx Employee
8,375 Views
Registered: ‎08-02-2007

hi,

 

if you would want to write into a BRAM, then you can use the memory_test application available at 

$EDK_Install\sw\lib\sw_apps\memory_test

 

just as a sanity check, you can use XMD commands after downloading the bitstream.

 

--> mwr 0x41218000 0xdeadbeef 0x10

--> mrd 0x41218000 0x10

 

--hs

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qwerty1234578
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I am run $EDK_Install\sw\lib\sw_apps\memory_test
and convinced again, that data dont write to the memory, test fail, command mwr and mrd show me

mwr 0x41218000 0xdeadbeef 0x10
XMD% mrd 0x41218000 0x10
41218000:   00000000
41218004:   00000000
41218008:   00000000
4121800C:   00000000
41218010:   00000000
41218014:   00000000
41218018:   00000000
4121801C:   00000000
41218020:   00000000
41218024:   00000000
41218028:   00000000
4121802C:   00000000
41218030:   00000000
41218034:   00000000
41218038:   00000000
4121803C:   00000000
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htsvn
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Registered: ‎08-02-2007

hi,

 

can you share the MHS of your design?

 

--hs

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qwerty1234578
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of corse

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htsvn
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

hi,

 

i have looked at the mhs and the BRAM ports are made external. are you trying to access the BRAM from external fabric?

 

--hs

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qwerty1234578
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yes, B port external, i am trying to access the BRAM from from fabric, none of this has happened.
if I connect both ports A and B of BRAM to the bram_controller in mb, read-write operations work correctly and tests passed.
what does it mean? my actions in fabric make memory unaccesseble? do you have an example how coorectly works with bram through external port? 

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qwerty1234578
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i am create design with PLB bus, instead of AXI. All work fine! Tests passed, I have access from microblaze and from fpga.
what of difference in the case of AXI bus?

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htsvn
Xilinx Employee
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Registered: ‎08-02-2007

hi,

 

glad that it works with plb. how are you handling the BRAM from the other logic?

--hs

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