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341 Views
Registered: ‎09-15-2019

Bare-Metal application works in JTAG mode, but not in Flash mode

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Hi,

I'm using ZED, and the bare-metal application works fine when it's loaded via JTAG. I'm able to control an ADC (connected to ZED through FMC connector) via I2C.
But, when i flash (QSPI) the application along with with fsbl, the application is running, but not able to read the control registers from the ADC.

Then I tried flashing, and debugged with XSDB. again, the application works fine when i reset the processor and run it. However, a normal power reset doesn't give me the same results. what could be the difference when running from JTAG and Flash, which is causing this discrepancy in the same application code  

Board - ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1)
Vivado - 2015.4.2

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138 Views
Registered: ‎09-15-2019

Hi, It turns out that, the 3.3V supply from the ZED (via FMC) to power up the ADC stabilizes only after some delay. Any communication during this time ends up failing. Once this is sorted out, the application works fine. Thanks !

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4 Replies
katsuki
Xilinx Employee
Xilinx Employee
268 Views
Registered: ‎11-05-2019

Hello anojhsna@gmail.com 

There is a difference whether the power is still on or not. Since the version of the tool you are using is older, we also recommend trying with the latest version.
Is the application running when booting from Flash? You can check it in the debug print output of the application.

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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250 Views
Registered: ‎09-15-2019

Hi Katsuki,

I'm using an old HDL design provided by Analog Devices, hence i'm stuck with the old VIVADO version. 

I checked the status of the application by adding UART outputs at different stages of my code, and i can see the application is running after the fsbl handoff. However, i don't get any debug information from fsbl, though i have defined FSBL_DEBUG_INFO.

But as i said, The fsbl debug information is printed when i reset the processor(after power on) and run with XSDB. below is the print,

Xilinx First Stage Boot Loader
Release 2015.4 Apr 12 2021-18:04:20
Devcfg driver initialized
Silicon Version 3.1
Boot mode is QSPI
Single Flash Information
FlashID=0x1 0x2 0x19
SPANSION 256M Bits
QSPI is in single flash connection
QSPI Init Done
Flash Base Address: 0xFC000000
Reboot status register: 0x60500000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x000933D8
Data Word Len: 0x000933D8
Partition Word Len:0x000933D8
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000065D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFE3FC36
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x00000A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x000933D8
PCAP DMA DEST LEN 0xF8007024: 0x000933D8
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x00008005
Data Word Len: 0x00008005
Partition Word Len:0x00008005
Load Addr: 0x00100000
Exec Addr: 0x00100000
Partition Start: 0x000999B0
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFD4E3CF
Application
Handoff Address: 0x00100000
In FsblHookBeforeHandoff function
SUCCESSFUL_HANDOFF
FSBL Status = 0x1

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katsuki
Xilinx Employee
Xilinx Employee
238 Views
Registered: ‎11-05-2019

Hi anojhsna@gmail.com 

You may want to embed a debug print in your application to see if the ADC is processing and initializing properly.

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
0 Kudos
139 Views
Registered: ‎09-15-2019

Hi, It turns out that, the 3.3V supply from the ZED (via FMC) to power up the ADC stabilizes only after some delay. Any communication during this time ends up failing. Once this is sorted out, the application works fine. Thanks !

View solution in original post