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Anonymous
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Bitstream is not compatible while programming FPGA

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Hello,

 

I have ZCU102, rev 1.0. I have created simple design when I try to turn on LED somewhat according to this tutorial: https://www.youtube.com/watch?v=8i8GLF-Md3U

 

Problem is, when I generate a bitstream and I try to program FPGA in SDK, I get "Bitstream is not compatible with the target revision, use -no-revision-check to allow programming."

 

Is there an explanation as to why is this happening? I have correctly chosen ZCU102 as target board in Vivado 2017.2.

 

Also, what does it mean to use -no-revision-check to allow programming? How do I do it? I have Windows, just a note.

 

Thank you.

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a_chami
Explorer
Explorer
14,695 Views
Registered: ‎04-12-2017

When you program the device under Vivado, if you receive an error message similar to this one:

 

"[Labtools 27-3303] Incorrect bitstream assigned to device. Bitstream was generated for part xcvu095-ffva2104-2-e, target device (with IDCODE revision 1) is compatible with es2 revision bitstreams.

To allow the bitstream to be programmed to the device, use "set_param xicom.use_bitstream_version_check false" tcl command."

 

Copy and paste the "set_param" command up to and including the "false" to your tcl command line on Vivado.

Hope this helps

 

Avi Chami MSc
FPGA Site

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a_chami
Explorer
Explorer
10,624 Views
Registered: ‎04-12-2017

There are several revisions for the device of ZCU102, like es1 and es2.

 

You can add them at install time (add engineering samples).

 

Anyway the message is not critical and when you receive the message you also receive the tcl command that you have to use to ignore this. Copy and paste it in the tcl command line (tcl tab).

Avi Chami MSc
FPGA Site
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Anonymous
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Thank you for your answer, tcl tab is to be found in SDK as XSCT?

 

Because if yes, then this command is unknown. It even seems to be more of a flag to some other command.

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a_chami
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Registered: ‎04-12-2017

Tcl tab is on Vivado tool

Avi Chami MSc
FPGA Site
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Anonymous
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10,600 Views
Thank you, but it still doesn't accept -no-revision-check. Not as single command, not as a flag to xsdk.
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Anonymous
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10,595 Views

I have found a workaround. I alternatively programmed FPGA using Hardware Manager. Problem with revision can be very simply and intuitively solved there.

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a_chami
Explorer
Explorer
14,696 Views
Registered: ‎04-12-2017

When you program the device under Vivado, if you receive an error message similar to this one:

 

"[Labtools 27-3303] Incorrect bitstream assigned to device. Bitstream was generated for part xcvu095-ffva2104-2-e, target device (with IDCODE revision 1) is compatible with es2 revision bitstreams.

To allow the bitstream to be programmed to the device, use "set_param xicom.use_bitstream_version_check false" tcl command."

 

Copy and paste the "set_param" command up to and including the "false" to your tcl command line on Vivado.

Hope this helps

 

Avi Chami MSc
FPGA Site

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tl_rtclancy
Observer
Observer
8,990 Views
Registered: ‎12-13-2017

Has anyone found an SDK solution to this problem. I understand the solution for Vivado and yes that works.  Unfortunately that is not helpful when running the SDK. When you run the SDK debugger it first attempts to download the file and produces the error message but I have not been able to determine where I need to go in the SDK to specify  -no-revision-check so that the SDK programmer does not fail.

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tl_rtclancy
Observer
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8,973 Views
Registered: ‎12-13-2017

I was able to workaround this in sdk by doing the following:

 

from pull downs xilinx->xsct console

 

xsct% targets
1* PS TAP
2 PMU
3 PL
4 MicroBlaze Debug Module at USER2
5 MicroBlaze #0 (Running)
6 PSU
7 RPU (Reset)
8 Cortex-R5 #0 (RPU Reset)
9 Cortex-R5 #1 (RPU Reset)
10 APU (L2 Cache Reset)
11 Cortex-A53 #0 (APU Reset)
12 Cortex-A53 #1 (APU Reset)
13 Cortex-A53 #2 (APU Reset)
14 Cortex-A53 #3 (APU Reset)
xsct% targets 5

 

xsct% fpga -f download.bit

bitstream is not compatible with the target revision, use -no-revision-check to allow programming

xsct% fpga -f download.bit -no-revision-check

initializing
0% 0MB 0.0MB/s ??:?? ETA
4% 1MB 2.2MB/s ??:?? ETA
7% 1MB 1.9MB/s ??:?? ETA

..

..

 

xsct% dow ../project_1/project_1.sdk/hw/Debug/hw.elf

 

at this point you can debug the software by going into "debug configurations" and in the "target setup" tab set the "debug type" to "attach to running target"

 

note: this was all done in 2017.3.

 

 

exragur
Observer
Observer
8,067 Views
Registered: ‎09-14-2017

I had the same issue with the ZCU102 Rev 1.0 Evaluation Board,

 

in the SDK you have to type in the xsct% fpga -file <path to bit-file> -no-revision-check.

 

Importan for Windows is the path, it is normaly like: Examplepath\Examplefile

 

you have to exchange the "\" by "/" that it works. I hope it helps.

 

Best regards,

 

Franz

 

note: tested with SDK 2017.4

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emcalnan
Observer
Observer
5,946 Views
Registered: ‎12-15-2014

Franz,

 

Thank you for posting the only intelligent answer. 

I could not figure out how to turn off BIT file checking in the Xilinx SDK and your solution worked perfectly with Xilnx SDK 2018.1.

 

Now I need to figure out how to give you 100 kudos...

 

Michael

mbrainin
Observer
Observer
5,498 Views
Registered: ‎04-18-2018

These solutions are great workarounds, but they do not solve the problem.

I've been able to load the FPGA via vivado or the SDK with the solutions posted above, but I still get the 'bitstream incompatible' error when I try to load with petalinux-boot.

Any solution or workaround for that?

 

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