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12ff7a6
Visitor
Visitor
818 Views
Registered: ‎01-29-2021

Blinking test on Ultra96 v2

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Hello everyone, 

I'm learning Zynq MP right now and I'm using Ultra96 v2. I knew Ultra96 v2 has 4 PS LEDs, so I have built a simple hardware design and activated GPIO MIO in I/O configuration. Then I have wirtten a C program in Vitis to try to control LED. But I got a Warning about FSBL from Vitis. Did i do something wrong? I have posted hardware design, code, Vitis log and warning below. Any help would be appreciated.

gpio.pngzynq_mp.pngwarning.png

#include "xgpiops.h"
#include "sleep.h"

int main(){
	static XGpioPs psGpioInstancePtr;
	XGpioPs_Config* GpioConfigPtr;
	int iPinNumber = 20;
	u32 uPinDirection = 0x1;
	int xStatus;
	//init
	GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PSU_GPIO_0_DEVICE_ID);
	if(GpioConfigPtr == NULL)
		return XST_FAILURE;
	xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr, GpioConfigPtr, GpioConfigPtr->BaseAddr);
	if(XST_FAILURE != xStatus)
		print("init failed \n\r");
	//set mio i/0
	XGpioPs_SetDirectionPin(&psGpioInstancePtr, iPinNumber, uPinDirection); //MIO direction
	XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, iPinNumber, 1); //MIO iPinNumber=20

	while(1){
		XGpioPs_WritePin(&psGpioInstancePtr, iPinNumber, 1);
		sleep(50000);
		XGpioPs_WritePin(&psGpioInstancePtr, iPinNumber, 0);
		sleep(50000);
}

return 0;
}
15:52:29 DEBUG	: Registering SDKStatusHandler to handle trace exceptions.
15:52:29 DEBUG	: Registered the core plugin as the backup plugin for storing repository paths.
15:52:29 INFO	: Launching XSCT server: xsct.bat -n  -interactive C:\Users\loven\workspace\temp_xsdb_launch_script.tcl
15:52:29 INFO	: XSCT server has started successfully.
15:52:29 INFO	: plnx-install-location is set to ''
15:52:29 INFO	: Successfully done setting XSCT server connection channel  
15:52:29 INFO	: Successfully done setting workspace for the tool. 
15:52:29 INFO	: Platform repository initialization has completed.
15:52:30 INFO	: Registering command handlers for Vitis TCF services
15:52:44 INFO	: Successfully done query RDI_DATADIR 
15:52:54 INFO	: Connected to target on host '127.0.0.1' and port '3121'.
15:52:56 INFO	: Jtag cable 'Avnet USB-to-JTAG/UART Pod V1 1234-oj1A' is selected.
15:52:56 INFO	: 'jtag frequency' command is executed.
15:52:56 INFO	: Sourcing of 'D:/Vitis/2020.1/scripts/vitis/util/zynqmp_utils.tcl' is done.
15:52:56 INFO	: Context for 'APU' is selected.
15:52:58 INFO	: System reset is completed.
15:53:01 INFO	: 'after 3000' command is executed.
15:53:01 INFO	: 'targets -set -filter {jtag_cable_name =~ "Avnet USB-to-JTAG/UART Pod V1 1234-oj1A" && level==0 && jtag_device_ctx=="jsn-USB-to-JTAG/UART Pod V1-1234-oj1A-14710093-0"}' command is executed.
15:53:05 INFO	: FPGA configured successfully with bitstream "C:/Users/loven/workspace/led_test/_ide/bitstream/design_1_wrapper.bit"
15:53:06 INFO	: Context for 'APU' is selected.
15:53:06 INFO	: Hardware design and registers information is loaded from 'C:/Users/loven/workspace/test_mio/export/test_mio/hw/design_1_wrapper.xsa'.
15:53:06 INFO	: 'configparams force-mem-access 1' command is executed.
15:53:06 INFO	: Context for 'APU' is selected.
15:53:06 INFO	: Boot mode is read from the target.
15:53:07 INFO	: Context for processor 'psu_cortexa53_0' is selected.
15:53:07 INFO	: Processor reset is completed for 'psu_cortexa53_0'.
15:53:07 INFO	: The application 'C:/Users/loven/workspace/test_mio/export/test_mio/sw/test_mio/boot/fsbl.elf' is downloaded to processor 'psu_cortexa53_0'.
15:53:08 INFO	: 'set bp_53_7_fsbl_bp [bpadd -addr &XFsbl_Exit]' command is executed.
15:54:08 WARN	: Exit breakpoint of FSBL (XFsbl_Exit) is not hit within allocated wait time of '60' seconds.
Note: To wait for a fixed amount of time specify the FSBL function as empty in launch configuration. Use 'IDE_FSBL_BP_HIT_WAIT_TIME' environment variable in launch configuration to modify the wait time (seconds).
Reason: timeout: target has not halted
15:54:08 INFO	: 'bpremove $bp_53_7_fsbl_bp' command is executed.
15:55:44 INFO	: ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source D:/Vitis/2020.1/scripts/vitis/util/zynqmp_utils.tcl
targets -set -nocase -filter {name =~"APU*"}
rst -system
after 3000
targets -set -filter {jtag_cable_name =~ "Avnet USB-to-JTAG/UART Pod V1 1234-oj1A" && level==0 && jtag_device_ctx=="jsn-USB-to-JTAG/UART Pod V1-1234-oj1A-14710093-0"}
fpga -file C:/Users/loven/workspace/led_test/_ide/bitstream/design_1_wrapper.bit
targets -set -nocase -filter {name =~"APU*"}
loadhw -hw C:/Users/loven/workspace/test_mio/export/test_mio/hw/design_1_wrapper.xsa -mem-ranges [list {0x80000000 0xbfffffff} {0x400000000 0x5ffffffff} {0x1000000000 0x7fffffffff}] -regs
configparams force-mem-access 1
targets -set -nocase -filter {name =~"APU*"}
set mode [expr [mrd -value 0xFF5E0200] & 0xf]
targets -set -nocase -filter {name =~ "*A53*#0"}
rst -processor
dow C:/Users/loven/workspace/test_mio/export/test_mio/sw/test_mio/boot/fsbl.elf
set bp_53_7_fsbl_bp [bpadd -addr &XFsbl_Exit]
con -block -timeout 60
bpremove $bp_53_7_fsbl_bp
----------------End of Script----------------

 

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1 Solution

Accepted Solutions
abouassi
Moderator
Moderator
629 Views
Registered: ‎03-25-2019

Hi @12ff7a6,

As mentioned in the link provided by @derekm_ , have you checked if you are using the right board filed definition file revision that match your board revision?
If yes, then it will be good to try to enable debug prints in FSBL to get further details from FSBL and see where it hangs exactly.
Check the different debug level here.

Best regards,
Abdallah
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derekm_
Voyager
Voyager
792 Views
Registered: ‎01-16-2019

It looks like you are setting up the Zynq configuration manually in Vivado, and I don't think you should be doing that. The first thing you need to do is get the board file for Ultra 96 V2 and add it to the board_files directory in Vivado, for example: C:\Xilinx\Vivado\2020.2\data\boards\board_files

I think this is where you can find what you need (depending on your version, 1.0 or 1.1): https://github.com/Avnet/bdf/tree/master/ultra96v2/1.1

You should add all the files to Vivado. Have a look at the directory structure and files for other boards, and just ensure you end up with something similar.

(Probably =>   C:\Xilinx\Vivado\2020.2\data\boards\board_files\ultra96v2\1.1\ )

Then, when you create your project, choose the ultra96v2 board.

Then, when you add the Zynq-7000 to the block diagram in IP Integrator, choose "Run Block Automation".

Only then should you start manually changing anything in the Zynq configuration, and only do that if you have a good idea of what you need to do.

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12ff7a6
Visitor
Visitor
780 Views
Registered: ‎01-29-2021

Hi Derekm_, thank you for your reply, I did exactly the same thing as you said. I have done several tests (hello world, peripheral, RAM) by using the Vitis templetes and a RAM r/w test. They all work pretty well, but this blinking test get me in trouble.

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derekm_
Voyager
Voyager
768 Views
Registered: ‎01-16-2019

Okay... Well, looking through your code, it looks fine. Your LED should be toggling. So your issue is not there.

Beyond that, I can't offer much more help, expect to point you to this post:

https://forums.xilinx.com/t5/Embedded-Development-Tools/Vitis-error-Exit-breakpoint-of-FSBL-not-hit/td-p/1149300

abouassi
Moderator
Moderator
630 Views
Registered: ‎03-25-2019

Hi @12ff7a6,

As mentioned in the link provided by @derekm_ , have you checked if you are using the right board filed definition file revision that match your board revision?
If yes, then it will be good to try to enable debug prints in FSBL to get further details from FSBL and see where it hangs exactly.
Check the different debug level here.

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post

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