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Registered: ‎09-16-2019

Block design RTL module pin planning issue

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Hello,

I am attempting to make a design that combines Xilinx IP with my own RTL module in the IP Integrator. I am having a problem with the two inputs into my RTL module:

bad_pins.JPG

 

During the writing of the bitstream I get the following error:

errorA.JPG

Now I understand the issue is that "clk" and "rst" pins are unassigned in the implementation but why is Vivado seeing these two pins as external when they are internal to the design? None of the other internal connections are doing this. Please help me rectify this issue.  

Thank you

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Registered: ‎09-16-2019

I figured out my issue. The problem was that I did not have the block design set as the top level in the sources. Once I made a wrapper for it and set it as the top source everything generated as expected. 

View solution in original post

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Highlighted
257 Views
Registered: ‎09-16-2019

I figured out my issue. The problem was that I did not have the block design set as the top level in the sources. Once I made a wrapper for it and set it as the top source everything generated as expected. 

View solution in original post

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