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Adventurer
Adventurer
4,262 Views
Registered: ‎07-20-2010

Building a ZynQ AXI Master Lite custom Peripheral in Vivado

Hi,

I am working with Zynq in Vivado 2014.2. I need to realize a custom peripheral with slave register on AXI Lite slave and AXI Master Lite capability. When I worked with EDK the Creator IP Wizard give me a vhdl template where there is AXI Lite IPIF, SOFT RESET and USER LOGIC. When I create IP with Vivado, IPIF is missing.

1) Is there documentation or reference design to build a custom IP with IPIF in the same style of EDK?

2) I have noticed that in the peripheral created by CIP in Vivado there is a difference about size of AXI_AWADDR e AXI_ARADDR. Using IPIF in EDK size is 32, in Vivado size is 6. If I insert IPIF how have to manage this size?

 

I have a lot of custom peripheral builded in EDK and I would port it in Vivado, without rewrite state machine that are using IPIF.  Can anyone help me?

Regards,

 

Begos

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Contributor
Contributor
423 Views
Registered: ‎07-17-2019

Hi,

      I  tried to build customized master peripheral for data transfering  b/w DDR and the master peripheral for ZC702(zynq) chip.But,it isnot working .please help me by providing some reference designs

Thanks in Advance

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Scholar
Scholar
402 Views
Registered: ‎05-21-2015

@mourya_chandra,

I'd be honoured to have the privilege of finding a bug or two in your current master design, assuming you'd be willing to share it.

Dan

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Contributor
Contributor
369 Views
Registered: ‎07-17-2019

@dgisselq

hi,

I attached my VHDL files ( I am using EDK 14.7)

 

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Contributor
Contributor
361 Views
Registered: ‎07-17-2019

Hi @dgisselq 

the code which i attached is working for reading(i didnt checked for writing)but it is reading garbage values.

Initially,using SDK i am writing values to the DDR memory(x0f000000 location ),after completion of writing to DDR I am sending one enable to Pl through GPIO and then the peripheral is reading but it is reading Garbage values

Thanks in Advance

 

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Scholar
Scholar
338 Views
Registered: ‎05-21-2015

@mourya_chandra,

I was hoping to be able to tell more, but for technical reasons I'm stuck deskchecking your code.

My best guess as to the reason why you are struggling is because your state machine doesn't line up with the control signals for the read data FIFO--at least that's what looks like it is going on from the state machines within your user_logic.vhd file.

I can also see why you are asking for an example AXI master.  You are going through a whole lot of work which would be much simpler (and cheaper) were you to write your own master.  Perhaps this bridge might encourage you.  It's how I handle talking to AXI, since most of my designs are written using Wishbone and not AXI.  This bridge gets me access to SDRAM.  There's also another Wishbone to AXI converter out there that handles only one transaction at a time, and uses the Wishbone classic mode instead of the Wishbone pipelined mode (above).  It'd be easier and simpler to use, although not nearly as fast since it only issues one command at a time, and the MIG DDR SDRAM IP you are intending to interact with tends to take 20+ clocks to return a result.

Dan

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Contributor
Contributor
314 Views
Registered: ‎07-17-2019

Hi @dgisselq 

   I will try that.

  Can you please tell me the frequency of BUS2IP_CLK ,I cant find it any where.

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Contributor
Contributor
312 Views
Registered: ‎07-17-2019

BUS2IP_CLK is coming from AXI_4LITE module . The frequency which is given to the AXI_4LITE module is 100 MHZ
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