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afilgueras
Contributor
Contributor
1,039 Views
Registered: ‎03-05-2014

CDMA interrupts not being enabled

Hi,


I'm having some problems using a cdma engine under linux.

Issue seems to be that the device driver does not successfully enable interrupts during module probe.

Therefore, any transfer will hang as the driver expects an interrupt in order to mark the transfer as finished.


During module probe, this is the sequence of reads/writes to the cdma register bank:

Read 0x00010002 from control reg (irqThreshold=1, TailPtrEn=1)
Write 0x00010006 to control reg (irqThreshold=1, Reset=1, TailPtrEn=1)
Read 0x00010002 from control reg 2 times (irqThreshold=1, TailPtrEn=1)
Write 0x00017002 to control reg (irqThreshold=1, ERR_IrqEn=1, Dly_IrqEn=1, IOC_irqEn=1, TailPtrEn=1)

If I manually read control and status registers when the SO finished booting I get:
0x00010002 from control reg (irqThreshold=1, TailPtrEn=1)
0x0001000a from status reg (IRQThresholdSts=1, SGIncld=1, Idle=1)

I expected last read from control register to be 0x00170002 as interrupts should be enabled.

However, if I manually enable these interrupt bits by directly writing to the control register, everythin works as expected.

I'm using vivado and petalinux 2019.1.

 

Thanks

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abommera
Xilinx Employee
Xilinx Employee
973 Views
Registered: ‎10-12-2018

Hi @afilgueras ,

Can you cross-check once that you have enabled the interrupt in your block design?
It would be great if you provide the screen shot of your block design and CDMA configuration.

Thanks & Regards
Anil B
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afilgueras
Contributor
Contributor
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Registered: ‎03-05-2014

I can't see where I can enable or disable interrupts for the cdma IP

Here is my current configuration:

 

Screenshot from 2020-02-27 11-22-14.png

Property                        Type     Read-only  Value
ALLOWED_SIM_MODELS              string*  true       rtl
CLASS                           string   true       bd_cell
CONFIG.C_ADDR_WIDTH             string   false      48
CONFIG.C_AXI_LITE_IS_ASYNC      string   true       0
CONFIG.C_DLYTMR_RESOLUTION      string   false      256
CONFIG.C_ENABLE_KEYHOLE         string   false      false
CONFIG.C_INCLUDE_DRE            string   false      1
CONFIG.C_INCLUDE_SF             string   false      0
CONFIG.C_INCLUDE_SG             string   false      1
CONFIG.C_M_AXI_DATA_WIDTH       string   false      64
CONFIG.C_M_AXI_MAX_BURST_LEN    string   false      8
CONFIG.C_READ_ADDR_PIPE_DEPTH   string   false      4
CONFIG.C_USE_DATAMOVER_LITE     string   false      0
CONFIG.C_WRITE_ADDR_PIPE_DEPTH  string   false      4
CONFIG.Component_Name           string   false      design_1_axi_cdma_0_0
LOCATION                        string   false      2 440 820
LOCK_UPGRADE                    bool     false      0
NAME                            string   false      axi_cdma_0
PATH                            string   true       /axi_cdma_0
SCREENSIZE                      string   false      240 136
SELECTED_SIM_MODEL              string   false      rtl
TYPE                            string   true       ip
VLNV                            string   true       xilinx.com:ip:axi_cdma:4.1

Also, my block design:

Screenshot from 2020-02-27 11-24-37.png

The device tree node I'm getting from petalinux:

dma@a0001000 {                                                 
    #dma-cells = <0x1>;
    clock-names = "m_axi_aclk", "s_axi_lite_aclk";
    clocks = <0x26 0x26>;
    compatible = "xlnx,axi-cdma-4.1", "xlnx,axi-cdma-1.00.a";
    interrupt-names = "cdma_introut";
    interrupt-parent = <0x4>;
    interrupts = <0x0 0x59 0x4>;
    reg = <0x0 0xa0001000 0x0 0x1000>;
    xlnx,addrwidth = <0x30>;
    xlnx,include-sg;
    phandle = <0x2d>;

    dma-channel@a0001000 {
        compatible = "xlnx,axi-cdma-channel";
        interrupts = <0x0 0x59 0x4>;
        xlnx,datawidth = <0x40>;
        xlnx,device-id = <0x0>;
        xlnx,include-dre;
        xlnx,max-burst-len = <0x8>;
    };
};

 

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abommera
Xilinx Employee
Xilinx Employee
916 Views
Registered: ‎10-12-2018

Hi @afilgueras ,

Thank you for providing the details!!

The interrupt line from CDMA hooked up to the PS in hardware as below screenshot and interrupt entry has been included in the device tree in your case. 

CDMA_capture.PNG

May I know how you are reading/writing DMA register while probing? Can you cross-check with the test procedure given in below wiki for CDMA interrupt flag enable?

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842337/Linux+Soft+DMA+Driver

 

Thanks & Regards
Anil B
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afilgueras
Contributor
Contributor
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Registered: ‎03-05-2014

Hi

I've tried running the dma test.

Something weird happens:

First run fails (timeout) but next runs succeed.

[ 4973.578801] dmatest: Started 1 threads using dma0chan0
[ 4975.608998] dmatest: dma0chan0-copy0: result #1: 'test timed out' with src_off=0x940 dst_off=0x1f8 len=0x2fa8 (0)
[ 4975.609007] dmatest: dma0chan0-copy0: summary 1 tests, 1 failures 0 iops 5 KB/s (0)
[ 4983.048436] dmatest: Started 1 threads using dma0chan0
[ 4983.048941] dmatest: dma0chan0-copy0: result #1: 'test passed' with src_off=0x1e0 dst_off=0x540 len=0x3a50 (0)
[ 4983.048949] dmatest: dma0chan0-copy0: summary 1 tests, 0 failures 11904 iops 166666 KB/s (0)
[ 5121.526291] dmatest: Started 1 threads using dma0chan0
[ 5121.526762] dmatest: dma0chan0-copy0: result #1: 'test passed' with src_off=0x2240 dst_off=0x730 len=0x1018 (0)
[ 5121.526770] dmatest: dma0chan0-copy0: summary 1 tests, 0 failures 17241 iops 68965 KB/s (0)
[ 6084.656930] dmatest: Started 1 threads using dma0chan0
[ 6084.657401] dmatest: dma0chan0-copy0: result #1: 'test passed' with src_off=0x1d20 dst_off=0x6e0 len=0x10e0 (0)
[ 6084.657409] dmatest: dma0chan0-copy0: summary 1 tests, 0 failures 17241 iops 68965 KB/s (0)

Find attached some ILA waveforms that I got from running this tests.

They contain read and write operations to the cdma register bank.

 

Note that the successful one one has the interrupts enabled in control register from the beginning while the failing ne does not.

Tests are performed straight after boot, so no other interaction with cdma is made.

 

Still not sure what's going on.

 

Thank you

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hgiannopoulos
Visitor
Visitor
763 Views
Registered: ‎02-26-2020

I seem to be having the same problem. Can we get some additional guidance on this one?

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