Cache Setting for BRAM, RAM, lwip and Dual Core Zynq-7000 project
I have some problems in setting my Dual-Core/TCP project on a Zynq-7020 (ZedBoard). Apperently, I'm not able to move data from DDR to BRAM with DCache enabled.
Here's the details of my project:
- I want to use both the CPUs: CPU0 is handling lwip and a TCP connection with a PC to receive data to be written on the DDR; CPU1 is managing the data tranfer from DDR to BRAM by using an AXI-CDMA and SimpleTransfer() function. On the PL I've set the AXI-CDMA to access the HP0 port of the Zynq-PS and to the related AXI-BRAM-Controller.
- To correctly use the TCP connection I need to keep enabled the Caches (at least the L1D cache, L2 may be turn off), otherwise the speed transfer will drop by 10 times.
My problem is that, with the Cache enabled, the SimpleTransfer() is not working and is not transfering the correct data. From what I got from the internet I understood that I must invoke DCacheFlush() or DCacheInvalidateRange() before the transfer. The problem is that the AXI-BRAM-Controller is not under the addresses of the Zynq-PS and invoking DCacheFlush with the AXI-BRAM-Controller addr is not allowed and will crash the software running (the function is trying to access an unknown/forbidden address). I already tried to flush/invalidate the DDR addresses of my data (which is allowed) but nothing changes.
Please note that the two cores must work at the same time. Therefore, disabling and enabling the cache is not a solution since will slow down the TCP performance of CPU0.
I was wondering if I have to move the AXI-BRAM-Controller under the Zynq-PS (i.e. connect it as a Slave of the PS instead of the CDMA) but I'm not sure about this solution and about the performances (all the examples and templates always put the AXI-BRAM-CONTROLLER under the CMDA control).