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dinaemadeldin
Observer
Observer
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Registered: ‎07-15-2020

Can ARM Master send data to mutiple AXI slave interfaces in parallel

I want to understand how Master port on PS part can send data transactions , can we run multiple threads in parallel to read or write multiple slaves at the same time?

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savula
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Registered: ‎10-30-2017

Hi @dinaemadeldin ,

It is not clearly mentioned which device you are using (Zynq or Zynq MPSoC). But in both the cases the the ARM master has cable to send data to the multiple slaves in parallel. this is tracked by AXI IDs.

Best Regards,
Srikanth
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dinaemadeldin
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Registered: ‎07-15-2020

can it work with AXI4 Lite as it hasn't AXI ID variable?

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savula
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Registered: ‎10-30-2017

Hi @dinaemadeldin ,

Please connect the AXI interconnect between ARM Master and AXI Slave IP. the Interconnect will take care of it.

Best Regards,
Srikanth
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dgisselq
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Registered: ‎05-21-2015

@dinaemadeldin,

I'm not sure @savula has been clear here: Any given master can send a single request to a single slave per clock cycle, sometimes not even that often.  To access multiple slaves, the requests will need to be made to each slave individually and serially.  One request will not be forwarded to multiple slaves in parallel.  What @savula is referencing is the fact that multiple requests may be ongoing at the same time, and multiple slaves may have transactions pending.  Even in this case, all requests to multiple slaves and their responses will be serialized--just not necessarily in issue order.

Suppose, therefore, that you wish to make a write request to slaves 0, 1, and 2.  The master cannot issue a single request to all three slaves.  Instead, it must issue a request to write to slave 0, another to write to slave 1, and then a third to write to slave 3.  These requests will all take place on different clock cycles.  Where things become concurrent is in the response.  The master may make all requests before any response comes back.  In this fashion, the requests may appear to be concurrent--even though the requests have been serialized.  Responses from the slaves may then be returned in any order--as long as the master used multiple ID's.  If all three requests were for the same AXI ID, then the interconnect would wait for the response from slave 0 before issuing the request to slave 1, etc.  If all three requests were made with different AXI IDs, then they might all be outstanding at the same time.

What about AXI4-lite?  The same rules apply--assuming you have a good AXI4->AXI4-lite bridge.  (Xilinx has been known to treat AXI4-lite as a second class citizen, and I've been told that if you want throughput you should be using AX4 and not AXI4-lite.)  If AXI4-lite is treated properly, there will be a bridge from AXI4 to AXI4-lite that will handle the AXI ID's for you and just quietly mirror the request ID's into the responses.  If you get stuck with Xilinx's AXI4->AXI4-lite area optimized conversion, specifically the one that only lets a single request through at a time, then your paint might dry before all of the request responses are returned.

Dan