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Visitor
Visitor
5,132 Views
Registered: ‎06-23-2011

Can't get full gigabit speed

Hi,


I'm using a hard Temac with a LocalLink Fifo on a Virtex-5, trying to send hardcoded 1500 Byte ethernet frames containing a UDP packet.  


However, using the following simple code I cannot seem to get above 280 Mbps:

 

     XLlTemac_Config *configEthernet;
     XLlTemac ethernet;
     XLlFifo fifo;

     int count;
     u32 frame_len;
     
     #define frame_size 1500
     
     u8 eth_frame[frame_size] =
     {
         // Ethernet
    	 0x00, 0x11, 0x22, 0x33, 0x44, 0x55,  // destination MAC
         0xAB, 0xCD, 0xEF, 0x12, 0x34, 0x56, //  source MAC
         0x08, 0x00, // ethertype : IP
         // IP Header
         0x45, 0x00, // Header Length
         0x05, 0xce, // Total IP Length (1500 - 14 from Eth = 1486)
         0x12, 0x34, // ID
         0x40, 0x00, // Fragment Flags
         0xff,       // Time to Live
         0x11,       // this is a UDP packet
         0x4c, 0x86, // IP Checksum
         10,0,1,255, // source IP
         10,0,1,102, // dest IP
         // UDP Header
         0xAA, 0xAA, // UDP Source Port
         0xBB, 0xBB, // UDP Dest Port
         0x05, 0xba, // UDP Length
         0x00, 0x00, // Checksum
     };
	 
     //Fill up UDP Data
     int udp_data_index;
     for(udp_data_index = 43; udp_data_index <= frame_size; udp_data_index++)
    	 eth_frame[udp_data_index] = 0xab;


     configEthernet = XLlTemac_LookupConfig(XPAR_LLTEMAC_0_DEVICE_ID);
     XLlTemac_CfgInitialize(&ethernet, configEthernet, XPAR_LLTEMAC_0_BASEADDR);

     XLlFifo_Initialize(&fifo, XPAR_XPS_LL_FIFO_0_BASEADDR);

     frame_len = sizeof(eth_frame);
	 
     while(1)
     {
          XLlFifo_Write(&fifo, eth_frame, frame_len);
          XLlFifo_TxSetLen(&fifo, frame_len);
     }

 Does anyone have any idea where the bottleneck could be, or how to achieve closer to a full gigabit throughput?

 

Thanks.

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4 Replies
Advisor
Advisor
5,109 Views
Registered: ‎12-03-2007

Hi,

 

(1) It looks like you're sending frames from a processor, and this slows things down. You'd need to profile the code to know how much. 

(2) There is some overhead due to the fact that UDP frames are not maximum size of 64KByte. But it's much less than (1).

 

 

Thanks,

Evgeni

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Xilinx Employee
Xilinx Employee
5,106 Views
Registered: ‎08-01-2007

Make sure you enable the cache.

 

If using MicroBlaze to feed the data from PLB, it's always single beat. That makes every packet takes about 600 us to send to the FIFO in my simulation.

 

When cache is enabled (refer to SDK Hello World example design), the smallest frame interval reduces to 3 us.

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Visitor
Visitor
5,081 Views
Registered: ‎06-23-2011

To enable the cache, it takes more than using the "init_platform" function from the Hello World example, correct?  The cache needs to be enabled on the microblaze as well, as shown here:

 

 

Can this BRAM be used for this, or must it come from externam memory?

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Xilinx Employee
Xilinx Employee
5,077 Views
Registered: ‎08-01-2007

Since you're using MicroBlaze, cache can only access the memory through XCL bus. BRAM Controller doesn't provide such an interface. xps_mch_emc and MPMC both have XCL bus.
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