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dinaemadeldin
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Registered: ‎07-15-2020

Can't latch input from PS to PL each clock cycle

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I try to simulate the my custom Buffer AXI IP using AXI VIP master , I got very strange behavior  I latch the input to "AXI4LITE_WRITE_BURST" each clock cycle but the output became delayed about 8 cycles every time , I removed all the conditions to pass written input from AXI to the PL but the delay didn't disappear ,

Can any one give me the reason for this?!

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dgisselq
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Registered: ‎05-21-2015

@dinaemadeldin,

Not knowing the rest of your design, it's kind of hard to tell.  In general, I know that Xilinx has chosen to treat AXI4-lite as a second class citizen bus protocol.  1) The interconnect is known for throttling AXI4-lite transactions.  That may account for 4 clocks.  2) Vivado's demonstration AXI4-lite logic core since about 2018.3 and into 2020.1 can only handle (at best) one write transaction every three clocks and one read transaction every other clock.  3) Vivado's demonstration AXI4 logic can't handle both read and write transactions that arrive at the same time, and only gets a 50% read throughput. 4) The stock AXI4-lite slave, that all of Xilinx's training materials are built upon, is broken.  It has been since 2016.3, and remains broken in Vivado 2020.1.  Whether or not it hangs your AXI bus will be dependent upon your interconnect configuration settings.

If you put all that together, that's an expected delay of between 6-7 clock cycles, and longer if you are doing reads and writes at the same time.

I'm not sure I can explain the 8th clock cycle though.

If you want throughput, you'll need to do a couple of things.  1) Switch from AXI4-lite to AXI4.  2) Switch from Xilinx's example designs to one that can handle 100% throughput.  3) Adjust your interconnect so that it is tuned for performance not area.  4) You may also need to adjust your cache settings within the CPU--but I'm not sure you've gotten that far yet in your project.

Dan

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dgisselq
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Registered: ‎05-21-2015

@dinaemadeldin,

Not knowing the rest of your design, it's kind of hard to tell.  In general, I know that Xilinx has chosen to treat AXI4-lite as a second class citizen bus protocol.  1) The interconnect is known for throttling AXI4-lite transactions.  That may account for 4 clocks.  2) Vivado's demonstration AXI4-lite logic core since about 2018.3 and into 2020.1 can only handle (at best) one write transaction every three clocks and one read transaction every other clock.  3) Vivado's demonstration AXI4 logic can't handle both read and write transactions that arrive at the same time, and only gets a 50% read throughput. 4) The stock AXI4-lite slave, that all of Xilinx's training materials are built upon, is broken.  It has been since 2016.3, and remains broken in Vivado 2020.1.  Whether or not it hangs your AXI bus will be dependent upon your interconnect configuration settings.

If you put all that together, that's an expected delay of between 6-7 clock cycles, and longer if you are doing reads and writes at the same time.

I'm not sure I can explain the 8th clock cycle though.

If you want throughput, you'll need to do a couple of things.  1) Switch from AXI4-lite to AXI4.  2) Switch from Xilinx's example designs to one that can handle 100% throughput.  3) Adjust your interconnect so that it is tuned for performance not area.  4) You may also need to adjust your cache settings within the CPU--but I'm not sure you've gotten that far yet in your project.

Dan

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dinaemadeldin
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Registered: ‎07-15-2020

Thanks for your answer , I have one more question I understand that I can't perform read and write at the same time, but can I write to multiple AXI4 Lite slaves at the same time.

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dinaemadeldin
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Registered: ‎07-15-2020
Thanks for your answer , I have one more question I understand that I can't perform read and write at the same time, but can I write to multiple AXI4 Lite slaves at the same time.
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dgisselq
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Registered: ‎05-21-2015

@dinaemadeldin,

According to AXI4 bus protocol, you can not only read and write at the same time, but you can also read and write to multiple slaves at the same time.  There's no problem doing so.

Whether or not you can get Xilinx's interconnect to issue multiple requests at once is in many ways dependent upon how you set it up.  If you set it up for performance mode, then it's supposed to be able to handle multiple requests at the same time--even returning results from different slaves (potentially) in an out of order manner.  If you set it up for minimum area ... then it won't do that.

I mentioned that Xilinx's demonstration AXI slave implementations have problems.  You might find this to be a better AXI-lite implementation--without the bugs Xilinx's implementations have.  Likewise, this is a better AXI (full) slave implementation--also without the bugs in Xilinx's cores.  Both of those implementations can handle 100% throughput.  They'll also have a much lower lag going through the core, so they'll lower your response time without needing to adjust the interconnect.

One other thing--crossing clock domains, or adjusting bus widths will also slow down the response time.  This part really depends upon how you set up your bus and interconnect.

Dan

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