11-03-2020 09:48 AM
I found the following VHDL code for an SPI master online. I would like to slow down the SPI clock frequency, but it seems it is tied to my FPGA clock. How could I modify this code to easily change the SPI clock frequency?
Thank you for the assistance.. The code is attached.
01-21-2021 11:25 AM
That code definitely takes the system clock in from whatever you connect to it (probably the FPGA clock you're referencing). You could try using a clock divider to lower the frequency and then provide it to this code. Or you could even add the clock divider in this component. I can't make any promises regarding the efficiency of the code in the link I sent, but at least you can see an idea.
Hope that helps,