Changing the clock frequency at run time?

[aminfar1]

I have connected microblaze processor to a custom IP. The custom IP should be able to work at a range of 50 to 95 MHz (with steps of 15 MHz, I mean 50, 65, 80, 95 MHz). I have some clock sources available on the board such as 40, 80, 125 MHz. The user should be able to set the clock frequency of the custom IP without needing to resynthesize the design. The frequency change can be done when the custom IP is idle. My problem is that I don't know how to change the clock frequency of the custom IP at runtime. I think a DCM module is not the answer of my problem since it is not possible to change the output clock of the DCM at runtime.

Any advice would be greatly appreciated.

[jmonteiro-dme]

You can allways do it by software and set the change in hardware (process sensible to all clock signals) accoording to the state of a user register that interfaces hardware and software that you define for this purpose.

Best,

JM

[aminfar1]

Hi JM,

Can you describe your solution in detail? It is unclear to me.

you mentioned "process sensible to all clock signals", but a FF can only be sensitive to one clock signal?!

what I have currently done is using a counter to create different clock frequnecies. Then, the user can choose the clock signal by the software.

always @(posedge clk_source)     //clk_source is the input clock
      clk_cnt <= clk_cnt + 1'b1;       // a 3-bit counter

assign clk = (clk_sel == 2'b00) ? clk_cnt[2] : ((clk_sel == 2'b01) ? clk_cnt[1] : ( (clk_sel == 2'b10) ? clk_cnt[0] : clk80 ) ) ;   
//clk_sel is set by the software

always @(posedge clk) 
   ........

But my method does not prioved enough flexibilty. For example, if clk_source is 100  MHz, I can only have 100, 50, 25, 12.5 MHz clock frequnecies. 

[bassman59]

---

aminfar1 wrote:

I have connected microblaze processor to a custom IP. The custom IP should be able to work at a range of 50 to 95 MHz (with steps of 15 MHz, I mean 50, 65, 80, 95 MHz). I have some clock sources available on the board such as 40, 80, 125 MHz. The user should be able to set the clock frequency of the custom IP without needing to resynthesize the design. The frequency change can be done when the custom IP is idle. My problem is that I don't know how to change the clock frequency of the custom IP at runtime. I think a DCM module is not the answer of my problem since it is not possible to change the output clock of the DCM at runtime.

Any advice would be greatly appreciated.

---

You need an external PLL clock synthesizer.

-a

[jprovidenza]

You don't mention what FPGA part you're using.  Different families have different clocking capabilities.

Do you need exactly the clock frequencies you mentioned?  Is pretty close OK?

John Providenza

[aminfar1]

John,

I am using virtex-5 LX110T.

Yes, it's OK.  I am not strict on it. :). Any thing close to it also works for me. 

In the begininig, I wanted to have a very small step, like 52, 56, 60, 64, 68 MHz, ...  But I think this is too complicated.

Thanks,

aminfar1

[jprovidenza]

The V5 has PLL's inside of it.  I believe they can be dynamically reporgrammed, though I've

never done it.  This may be an easy path to solve your problem.

John Providenza

[barriet]

V5 has a DRP (dynamic reconfiguration port) on the DCM and PLL.

The DCM is described in the user guide.

While the PLL is also described there from a general functional perspective, you must get its DRP information from tech support:

http://www.xilinx.com/support/answers/24486.htm (Virtex-5 - What are the addresses and values for dynamic reconfiguration of the DCM or PLL through the DRP?)

It also recommended to review the datasheet (ds202 for V5) to review the associated parameters for the CMT (PLL + 2 DCM) block.

bt

[Anonymous]

• Changing the DCM clock output frequency is possible in runtime by using DRP. But please note that it requires reset after changing clocks.
• More details of DRP operation and usage you can get details in Chapter-5 (Page 107) of ug191.pdf
• Please not that the V-5 DRP only allows changes to M/D values. But Phase shift is not supported through DRP. Also the write part of the DRP does not work during simulation of DCM_Adv
•   DCM DRP information has been added to the Virtex-5 FPGA Configuration Guide. The V-5 user guide currently not provided DRP addresses  for PLL. The addresses and values for PLL user DRP can get by creating web case.  

Open Web Case

http://www.xilinx.com/support/clearexpress/websupport.htm

[sonicwave]

If you're not strict on the periods being the same for each clock cycle either, you might be able to get away with a fancy clock enable scheme of some sort? If you then run the design on a 100 MHz clock, you can just pull your clock enable low every tenth clock cycle for effectively a 90 MHz clock, every fifth for an 80 MHz clock, and so on.

I can think of quite a few cases where this won't work at all, but maybe your design isn't one of them?...;)