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Participant
Participant
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Registered: ‎07-05-2019

Changing the values of DDRC Module register in psu_init

Hello,

I am working on the ZCU102 board. In the Zynq Ultrascale+ PS IP of block design, I am using the default DDR settings. However, these settings do not contain information about how the DDR scheduler or controller works. In Xilinx SDK, the psu_init.c file contains all the default values that are in the DDRC Module registers. How do I change these default values? Can I modify the psu_init.c file and psu_init.tcl file? What steps do I need to take care of in order to achieve this? For example, in UG 1087, I need to change the default of register SCHED at location 0xFD070254 from 0x0 to 0x20.

Any help is appreciated.

Thanks,

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Visitor
Visitor
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Registered: ‎09-02-2020

Hello,

I'm also trying to customize DDRC Module register in psu_init. However, I'm not very clear for the PSU_Mask_Write function. If you already have the experiences, could you help me for this?

Thanks

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