Changing the values of DDRC Module register in psu_init
I am working on the ZCU102 board. In the Zynq Ultrascale+ PS IP of block design, I am using the default DDR settings. However, these settings do not contain information about how the DDR scheduler or controller works. In Xilinx SDK, the psu_init.c file contains all the default values that are in the DDRC Module registers. How do I change these default values? Can I modify the psu_init.c file and psu_init.tcl file? What steps do I need to take care of in order to achieve this? For example, in UG 1087, I need to change the default of register SCHED at location 0xFD070254 from 0x0 to 0x20.