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Registered: ‎03-21-2019

Clock Domain Synchronization of General Purpose Inputs to MIO pins in Zynq

The Zynq Technical Reference Manual says the following for the GPIO module:  "The controller is clocked by the CPU_1x clock from the APB interface. All outputs and input sampling is done using the CPU_1x clock."

My first question is, are the MIO inputs to the GPIO module in the Zynq PS synchronized to the CPU_1x clock before they are sampled?  If so, how are they synchronized?  Is a standard dual flip-flop synchronizer used?

My second question is, if the GPIO inputs are not synchronized to the CPU_1x clock before sampling, how do I get access to the CPU_1x within the PL so that I can synchronize them myself?

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