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diverger
Adventurer
Adventurer
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Registered: ‎06-22-2018

Clocking Wizard CLKOUT4 reconfig with PS code

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On Zynq-7, my configuration of Clocking Wizard is as below:

  1. Enable AXI lite interface.
  2. Enable CLKOUT4_CASCADE, and use CLKOUT4 as output, and with a default dividing of 2

And it works well after power on. The clock output is with correct frequency as designed. But I just can't change the output frequency with PS code. The code flow is as below:

  1. write '1' to offset 0x238, the divide register of CLKOUT4, and expect the output frequency will be doubled
  2. write '3' to offset 0x25C
  3. check the lock bit

The result is the output goes constant high.

Any help. Thanks.

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diverger
Adventurer
Adventurer
215 Views
Registered: ‎06-22-2018

I finally make it work. But with 'Write DRP registers' enabled. It seems there is an 'undocumented' feature, you should set the 'MX' bits of the reg2 of clk4 to '10b' to maintain the 'cascading' of clk4 and clk6. So the new register value written to reg2 should be the value shown in 'DRP Register' tab of Clocking Wizard ored by 0x0200. 

I have not figure out how to check the locked status by reading DRP register. But it's trivial by reading an AXI GPIO pin connected to 'locked' pin to check it. 

Cheers! And if there are other methods, please tell me :).

View solution in original post

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diverger
Adventurer
Adventurer
216 Views
Registered: ‎06-22-2018

I finally make it work. But with 'Write DRP registers' enabled. It seems there is an 'undocumented' feature, you should set the 'MX' bits of the reg2 of clk4 to '10b' to maintain the 'cascading' of clk4 and clk6. So the new register value written to reg2 should be the value shown in 'DRP Register' tab of Clocking Wizard ored by 0x0200. 

I have not figure out how to check the locked status by reading DRP register. But it's trivial by reading an AXI GPIO pin connected to 'locked' pin to check it. 

Cheers! And if there are other methods, please tell me :).

View solution in original post