Clocking Wizard: Dynamic change of output frequency without interruption of the clock - possible?
I have to set up a 50 MHz clock source whose frequency can be varied by small amounts (about 0.1% per change operation) without interrupting the generated clock signal. Reconfiguring a Clocking Wizard 6.0 over AXI4-Lite via the driver (according to the procedure on page 55 of the Clocking Wizard 6.0 product guide) works fine for me, however the output clock appears to be interrupted for a short period after triggering the configuration.
Is there any way to avoid this interruption? Of course the fallback solution would be a tuneable clock source outside the FPGA, but I want to avoid this if possible. I'm using a ZynQ XC7Z020 (on a PyNQ-Z1 board).