cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
vms1966
Newbie
Newbie
215 Views
Registered: ‎02-20-2020

Clocking Wizard: Dynamic change of output frequency without interruption of the clock - possible?

Hello,

I have to set up a 50 MHz clock source whose frequency can be varied by small amounts (about 0.1% per change operation) without interrupting the generated clock signal. Reconfiguring a  Clocking Wizard 6.0 over AXI4-Lite via the driver (according to the procedure on page 55 of the Clocking Wizard 6.0 product guide) works fine for me, however the output clock appears to be interrupted for a short period after triggering the configuration.

Is there any way to avoid this interruption? Of course the fallback solution would be a tuneable clock source outside the FPGA, but I want to avoid this if possible. I'm using a ZynQ XC7Z020 (on a PyNQ-Z1 board).

Thanks for any help!

Cheers, Matt

 

Tags (3)
0 Kudos
1 Reply
dgisselq
Scholar
Scholar
115 Views
Registered: ‎05-21-2015

@vms1966 ,

Here's another solution that allows you to fine tune a clock.  It requires an external pin and some logic, but the resulting "clock" can then be fed into the PLL and allowed to be tuned.

Dan

0 Kudos