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golson
Scholar
Scholar
8,308 Views
Registered: ‎04-07-2008

Configure Xilkernal & lwip

Hi,
  I get the following errors trying to create the BSP
 
I am trying to configure my design Xikernal and lwip library.  I chose to use
a soft EMAC to start.
 
Any help is appreciated. Thank You,
Gary Olson
 
 
 
Performing Clock DRCs...
WARNING:MDT - C:\BSB_PRACTICE\LWIP_ONE\system.mss line 23 - PARAMETER
   config_elf_process is deprecated !. .
   To avoid seeing this Warning again, please remove PARAMETER
   config_elf_process.
ERROR:MDT - C:\BSB_PRACTICE\LWIP_ONE\ line 0 - Peripheral instance Ethernet_MAC
   is not a valid IP for PARAMETER emaclite_instname !
ERROR:MDT - Errors occured while creating Software System
Done!
 
 

 PARAMETER VERSION = 2.2.0

BEGIN OS
 PARAMETER OS_NAME = xilkernel
 PARAMETER OS_VER = 4.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER sysintc_spec = xps_intc_0
 PARAMETER stdout = RS232_Uart_1
 PARAMETER stdin = RS232_Uart_1
 PARAMETER config_debug_support = true
 PARAMETER debug_mon = true
 PARAMETER verbose = true
 PARAMETER config_sema = true
 PARAMETER max_sem_waitq = 100
 PARAMETER config_time = true
 PARAMETER max_tmrs = 100
 PARAMETER max_readyq = 100
 PARAMETER pthread_stack_size = 5000
 PARAMETER max_pthreads = 50
 PARAMETER systmr_dev = xps_timer_1
 PARAMETER config_elf_process = true
 PARAMETER static_elf_process_table = ((socket_thread,1),(dummy_thread,1))
 PARAMETER static_pthread_table = ((socket_thread,1),(dummy_thread,1))
END

BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.11.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = lmb_bram
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.12.a
 PARAMETER HW_INSTANCE = RS232_Uart_1
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = emc
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = SRAM
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = emaclite
 PARAMETER DRIVER_VER = 1.12.a
 PARAMETER HW_INSTANCE = Ethernet_MAC
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.10.b
 PARAMETER HW_INSTANCE = xps_timer_1
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = SRAM_util_bus_split_1
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = clock_generator_0
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.12.a
 PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = proc_sys_reset_0
END
BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.10.c
 PARAMETER HW_INSTANCE = xps_intc_0
END

BEGIN LIBRARY
 PARAMETER LIBRARY_NAME = lwip
 PARAMETER LIBRARY_VER = 2.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER api_mode = SOCKETS_API
 PARAMETER emaclite_instances = ((Ethernet_MAC,0,0,0,0,0,0))
END
 
 
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15
# Wed Apr 09 12:43:13 2008
# Target Board:  Xilinx Virtex 5 ML505 Evaluation Platform Rev 1
# Family:    virtex5
# Device:    xc5vlx50t
# Package:   ff1136
# Speed Grade:  -1
# Processor: microblaze_0
# System clock frequency: 125.00 MHz
# On Chip Memory :  64 KB
# Total Off Chip Memory :   1 MB
# - SRAM =   1 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0

 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [7:30]
 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O
 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O
 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O
 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_SRAM_CLK = ZBT_CLK_OUT_s, DIR = O
 PORT fpga_0_SRAM_CLK_FB = ZBT_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.10.a
 PARAMETER C_DEBUG_ENABLED = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
 PORT Interrupt = Interrupt
END
BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.02.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 125000000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END
BEGIN xps_mch_emc
 PARAMETER INSTANCE = SRAM
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 8000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_THZOE_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER C_MEM0_BASEADDR = 0x84100000
 PARAMETER C_MEM0_HIGHADDR = 0x841fffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Mem_A = fpga_0_SRAM_Mem_A_split
 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN
END
BEGIN xps_ethernetlite
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_SPLB_CLK_PERIOD_PS = 8000
 PARAMETER C_BASEADDR = 0x81000000
 PARAMETER C_HIGHADDR = 0x8100ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
END
BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x84088000
 PARAMETER C_HIGHADDR = 0x8408ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = xps_timer_1_Interrupt
END
BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM_util_bus_split_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 7
 PARAMETER C_SPLIT = 31
 PORT Sig = fpga_0_SRAM_Mem_A_split
 PORT Out1 = fpga_0_SRAM_Mem_A
END
BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKFBIN_FREQ = 125000000
 PARAMETER C_CLKFBOUT_FREQ = 125000000
 PARAMETER C_CLKFBOUT_BUF = TRUE
 PORT CLKOUT0 = sys_clk_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
 PORT CLKFBIN = ZBT_CLK_FB_s
 PORT CLKFBOUT = ZBT_CLK_OUT_s
END
BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Peripheral_Reset = sys_periph_reset
END
BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = xps_timer_1_Interrupt
END
 

 
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1 Reply
centaur19
Xilinx Employee
Xilinx Employee
8,294 Views
Registered: ‎08-01-2007

You have to use Lwip v3.00.a with Xilkernel v4.00.a or Lwip v2.00.a with Xilkernel v3.00.a. Lwip v2.00.a is not compatible with the newer ethernet cores and similarly the v3.00.a is not compatible with the older ethernet cores.

The error that you get just indicates that it does not recognize the core (xps_ethernetlite) to be a supported Ethernet core.

You could also use the hard TEMAC on the Virtex 5 LXT device instead of the lite version :-)
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