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xilinxcocuk
Adventurer
Adventurer
527 Views
Registered: ‎11-06-2020

Control GPIOs with RTL and use microblaze

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Hello, I wonder if a "normal" RTL and a microblaze design can run at the same time inside the FPGA. I created a simple microblaze design with a UART interface and generated the HDL wrapper.
I also created a simple VHDL file to control 4 LEDs with 4 switches:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Test is
Port
(
clk: in std_logic;
sw: in std_logic_vector (3 downto 0);
led: out std_logic_vector (3 downto 0)
);
end Test;

architecture Behavioral of Test is

begin
process(clk)
begin
if(rising_edge(clk)) then
led (3 downto 0) <= sw (3 downto 0);
end if;
end process;
end Behavioral;

I integrated the switched and LEDs in the generated microblaze wrapper:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity uBlaze_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
led : out std_logic_vector (3 downto 0);
sw: in std_logic_vector (3 downto 0)
);
end uBlaze_wrapper;

architecture STRUCTURE of uBlaze_wrapper is
component uBlaze is
port (
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
sys_clock : in STD_LOGIC;
reset : in STD_LOGIC
);
end component uBlaze;

component Test is
port (
led : out std_logic_vector (3 downto 0);
sw: in std_logic_vector (3 downto 0)
);
end component Test;
begin
uBlaze_i: component uBlaze
port map (
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);

Testc: component Test
port map (
sw => sw,
led => led
);


end STRUCTURE;

 

But when I launch VITIS and program the FPGA I am possible to use UART. But can't control the LEDs with the switches.
Can anybody please explain?


 

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1 Solution

Accepted Solutions
joancab
Teacher
Teacher
513 Views
Registered: ‎05-11-2015

Yes, of course RTL and soft processors can run concurrently.

Did you assign pins to those inputs and outputs in a constraints file?

So you created your MB on a block diagram, generated the wrapper, left it as top HDL file and modify it. Did you re-run synthesis and implement after the modification?

Another way is to drag anddrop your VHDL/ Verilog file into the block diagram with the MB. When you generate the wrapper it will have I/Os for both. In theory it should be the same, I just prefer not to change auto-generated things, remember that Vivado auto-updates the wrapper so it may override your modifications.

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3 Replies
joancab
Teacher
Teacher
514 Views
Registered: ‎05-11-2015

Yes, of course RTL and soft processors can run concurrently.

Did you assign pins to those inputs and outputs in a constraints file?

So you created your MB on a block diagram, generated the wrapper, left it as top HDL file and modify it. Did you re-run synthesis and implement after the modification?

Another way is to drag anddrop your VHDL/ Verilog file into the block diagram with the MB. When you generate the wrapper it will have I/Os for both. In theory it should be the same, I just prefer not to change auto-generated things, remember that Vivado auto-updates the wrapper so it may override your modifications.

View solution in original post

xilinxcocuk
Adventurer
Adventurer
500 Views
Registered: ‎11-06-2020

@joancab thanks for your advice. I will try it like this and let you know

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xilinxcocuk
Adventurer
Adventurer
478 Views
Registered: ‎11-06-2020

@joancab now it works. I created the block design and just dragged the VHDL file into the block design as you said. I had to create input and output ports for the VHDL file block (right click on IP and create new port). Thanks!

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