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Contributor
Contributor
3,353 Views
Registered: ‎02-18-2008

Controlling one microblaze with another...

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Hi,

 

I'm trying to design a system with two microblazes(uB).

 

One uB will sort of be a master(MuB) and the other a slave(SuB) in the sense that the MuB will be responsible for writing the instructions to the instruction memory of the SuB. To do this, I separated out the data and instruction memories of the SuB. Both those memories are dual port BRAMS. I wrote a simple program to test this configuration that simply writes some values to a shared BRAM. The MuB reads the values and displays them through the UART. All this works fine.

 

However, as soon as I attach the Port Bs of the SuB data and instruction BRAMs to the plb bus of the MuB, the SuB stops working. No change to the software yet, both uBs still have their separate programs.  Is a block ram with two different kinds of controllers (an LMB controller and an XPS_bram_controller) not supported or are there some other fundamental problems with this configuration?

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Xilinx Employee
Xilinx Employee
4,147 Views
Registered: ‎08-06-2007

Hi,

 

MicroBlaze requires that instruction memory can be read/written by the data side.

The lmb memory that you have on the dp_microblaze violates that.

It makes it impossible to download code since that is done from the data interface to the instruction memory.

It also makes it harder to handle the linker scripts.

 

My advice is don't share LMB, you already have shared plb memory and you can use that for this purpose.

 

Göran

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Xilinx Employee
Xilinx Employee
3,338 Views
Registered: ‎08-06-2007

Hi,

 

Hard to tell without knowing how you have connected the system.

Ex. What is port Bs of SubData?

 

Please provide the .mhs file to make it easier to understand what you are trying to do?

 

Göran

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Contributor
Contributor
3,335 Views
Registered: ‎02-18-2008

Hey,

 

Here's the .mhs file. Confusingly, the MuB I talked about is called the sp_microblaze and the SuB is called the dp_microblaze in the design.

 

Just by connecting sp2dp_iplb_cntlr and sp2dp_dplb_cntlr to the instruction and data memories of the slave microblaze (dp_ilmb_bram and dp_dlmb_bram) seems to make the slave microblaze not execute its instructions.

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Xilinx Employee
Xilinx Employee
4,148 Views
Registered: ‎08-06-2007

Hi,

 

MicroBlaze requires that instruction memory can be read/written by the data side.

The lmb memory that you have on the dp_microblaze violates that.

It makes it impossible to download code since that is done from the data interface to the instruction memory.

It also makes it harder to handle the linker scripts.

 

My advice is don't share LMB, you already have shared plb memory and you can use that for this purpose.

 

Göran

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