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Registered: ‎11-17-2009

Controlling the delay between chip select becoming active and first clock pulse in axi quad spi

I have a block diagram design consisting (amongst other things) of a Zynq processor interfaced to a SPI based rotary encoder device via an axi_quad_spi peripheral in standard mode.

The ext spi clock is set at 100 MHz and I have a clock dividing factor of 32 - resulting in a 3.125 MHz spi clock.

The issue that I am having is that this particular encoder requries a minimum time of t(s) = 1250 ns delay between the chip select SS becoming active (i.e. going low) and the first clock pulse.  This t(s) delay is required for the rotary encoder to prepare the data that can subsequently be shifted out on the MISO output.A value less than 1250 ns results in corrupted data being transfered.

I have measured the default delay t(s) in my system and it is 600 ns - i.e. way too short.

The AXI Quad Spi datasheet does address this issue. So the question is - how can I  increase this delay?


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