cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
stoned49th
Newbie
Newbie
1,763 Views
Registered: ‎04-11-2010

Custom IP Read PFIFO Question

Hi, I'm quite new to FPGA's an heres my question on how to acces a Read PFIFO in an audio-input custom ip for the plb bus. I try to write two audio channels in one packet and acces it later in the software. I didn't have the time to test it yet, I just wantet you guys here to have a look at it, to see if I've done something substantially wrong. Heres the snippet from the user_logic.vhl:

 

 

Post_to_FIFO:process (Bus2IP_Clk) is
	variable status : integer range 0 to 20 := 0;
  begin
  	  if rising_edge(Bus2IP_Clk) then
			
	  		if (a_left_ready='1' and a_right_ready='1') then 
				case status is
					when 0 =>
						IP2RFIFO_WrMark <= '1'; 
						status := status + 1;
					when 1 => 
						IP2RFIFO_WrMark <= '0';
						IP2RFIFO_WrReq <= '1';
						IP2RFIFO_Data <= audio_data_l; 
						status := status + 1;
					when 2 =>
						if (RFIFO2IP_WrAck='1') then
							IP2RFIFO_Data <= audio_data_r;
							status := status + 1; 
						end if;
					when 3 =>
						if (RFIFO2IP_WrAck='1') then
							IP2RFIFO_WrReq <= '0'; 
							status := 0; 
							a_left_ready := '0';
							a_right_ready := '0';
						end if;
				end case;				
			else			
			IP2RFIFO_WrReq <= '0';
			IP2RFIFO_Data <= "00000000000000000000000000000000";
			IP2RFIFO_WrMark <= '0';
			IP2RFIFO_WrRelease <= '0';
			IP2RFIFO_WrRestore <= '0';			
			end if;	  
	  end if;
  end process Post_to_FIFO;

 

Thanks,

Lukas

0 Kudos
0 Replies