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diegosantibanez
Participant
Participant
646 Views
Registered: ‎07-25-2017

Custom IP block functional missmatch between simulation and ILA

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Hello,

 

I have been working on a simple custom VHDL Core that adds a TLAST pulse to an AXI Stream bus every N Data received (N is set via AXI Lite bus).

My problem is: When I simulat ethe block (functional and post place & route simulation) everything works fine, but when I "listen" to the AXI Stream signal using an ILA, the behievour changes.

 

How does it change?

- TLAST appears, but not every N data received.

- TLAST appears, but sometimes it lasts more than 1 clock cycle.

 

I would usually think that my code is just wrong, but my simulation seems ok, so I'n kind of stucked.

My question is: What kind of things cause a block simulation and its real behievour to be different?

 

 

I add here both, VHDL code, simulation and ILA waveforms:

 

Block CODE:

process (CTRL_ACLK, CTRL_ARESET_N)
begin
if CTRL_ARESET_N = '0' then

    tdata_reg_out <= (others => '0');
    tstrb_reg_out <= (others => '0');
    tlast_reg_out <=  '0';
    tvalid_reg_out <= '0';
    tready_reg_out <= '0';
    counter <= (others => '0');
   
 else
  if rising_edge(CTRL_ACLK) then
 
    if tvalid_reg = '1' then
      if tready_reg = '1' then
         if counter >= (reg_0 - 1) then
     
             tdata_reg_out <= tdata_reg;
             tstrb_reg_out <= tstrb_reg;
             tlast_reg_out <= '1';
             tvalid_reg_out <= tvalid_reg;
             tready_reg_out <= tready_reg;
             counter <= (others => '0');
          else
             tdata_reg_out <= tdata_reg;
             tstrb_reg_out <= tstrb_reg;
             tlast_reg_out <= '0';
             tvalid_reg_out <= tvalid_reg;
             tready_reg_out <= tready_reg;
             counter <= counter + 1;
         
          end if;
         end if;
     end if; 
   end if;
  end if;

end process;

 

SIMULATION

simulation.PNGILA.PNG

Thank you.

 

 

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diegosantibanez
Participant
Participant
586 Views
Registered: ‎07-25-2017

Thanks a lot for your answer Caleb.

I managed to solve the problem a few days ago and I had no time to update this post :)

It was an issue related to CLK sources. The way I usually implement an AXI Lite is using the wizard drivers that Xilinx provides. I create a core block afterwards, and I connect my top block, AXI block and core block all together.

My Custom IP Core had to use different CLK sources in their AXI and AXIS buses, and I thought it was enough "CLK isolation" to build the system that way.

It wasn't.

I had to "double register" AXI signals in my core block, because it was causing sync problems

So yea, basically I was simulating a block with a single CLK source, and I should've used 2 different ones.

 

 

Thanks for your time!

 

Diego.

 

View solution in original post

3 Replies
calebd
Moderator
Moderator
593 Views
Registered: ‎01-09-2019

Hello @diegosantibanez

The first thing that stands out to me is the inclusion of the ILA.  Are you/have you simulated the design while the ILA is included in the BD?  Since the ILA takes some physical resources, there may be changes to how Vivado does the implementation of the design with the ILA included.  This could give changes in the end result.  If the physical design is different (like including an ILA), that could cause differences in timing or implementation.

You mentioned that you are simulating post-place and route.  May I ask how you are doing that?  Vivado's simulator does not seem to default to using the post-place and route files even after the design has gone through that step.  I believe it will still default back to your block diagram/design files.

The things that usually cause a simulation and actual implementation to be different are related to assumptions made in simulation that can't be made when the design is implemented.  This usually is related to a hardware limitation like a timing violation or requirement, or a different skew value than what is used in simulation.  It could also be a variety of other issues that cause the difference.  Is there any timing issues/errors while in the process of generating the bitstream (or even a warning)?

Thank you,

Caleb

Thanks,

Caleb


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diegosantibanez
Participant
Participant
587 Views
Registered: ‎07-25-2017

Thanks a lot for your answer Caleb.

I managed to solve the problem a few days ago and I had no time to update this post :)

It was an issue related to CLK sources. The way I usually implement an AXI Lite is using the wizard drivers that Xilinx provides. I create a core block afterwards, and I connect my top block, AXI block and core block all together.

My Custom IP Core had to use different CLK sources in their AXI and AXIS buses, and I thought it was enough "CLK isolation" to build the system that way.

It wasn't.

I had to "double register" AXI signals in my core block, because it was causing sync problems

So yea, basically I was simulating a block with a single CLK source, and I should've used 2 different ones.

 

 

Thanks for your time!

 

Diego.

 

View solution in original post

calebd
Moderator
Moderator
581 Views
Registered: ‎01-09-2019

@diegosantibanez

Im glad you found a solution that fixed your issue.

Thank you for replying back with what was causing your problem, and the steps you took to fix it.

Caleb

Thanks,

Caleb


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

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