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dman
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Registered: ‎08-22-2016

Custom IP with AXI Stream input and ouput

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Hi everyone,

 

I'm trying to package the  project I made (a hash function) using the 'Create and package IP' functionality of Vivado (2015.3). In the popup window I select a S_AXIS and a M_AXIS port for my IP. Now, I want to add my hash function to this IP-block. But my question is: Where to do this ?

The resulted editing-project that opens, contains one (upper) file ...-arch_imp, and two files S/M_AXIS_inst one for each AXIS connection I made. If I were to declare and instantiate my function in one of the S/M_AXIS_inst files, I would not be able to reach either the input or the output connection. So, I assume that the upper file is the correct file to declare and instantiate my function in ? But, doesn't this negate the function of the other files ? Do I need to do the handshaking myself then ?

 

The inputs and outputs of my function:

clk         : in  std_logic;                    
rst_n       : in  std_logic;                    
din         : in  std_logic_vector(31 downto 0);
din_valid   : in std_logic;       

ready_at_output : in std_logic;             
buffer_full : out std_logic;      //Will not be used at the output             
ready       : out std_logic;     
dout        : out std_logic_vector(31 downto 0);
dout_valid  : out std_logic;                    
last_block : out std_logic;      //Denotes when the last block is given at the output

 

For the connections, I have a clue on how to do these, but correct me if I'm wrong.

clk   => s00_axis_aclk,     
rst_n    => s00_axis_aresetn,
ready    => s00_axis_tready,
din    => s00_axis_tdata,  
din_valid    => s00_axis_tvalid

 

dout_valid   => m00_axis_tvalid,
dout    => m00_axis_tdata,   
"0000"    => m00_axis_tstrb,   //Uncertain about this one
last_block  => m00_axis_tlast,   
ready_at_output   => m00_axis_tready 

 

Thanks in advance,

 

Dman

 

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muzaffer
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Teacher
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Registered: ‎03-31-2012
It seems like you're implementing the axis master within your IP. In that case you don't need the axis master block anymore. Actually you don't need the axis slave either as you are consuming s00_axis_tvalid/tdata and producing the s00_axis_tready so you have a full slave, compute, master block already.
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muzaffer
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Registered: ‎03-31-2012

I think the right place is the top level module. The master & slave streams just have the stream interfaces on one side which get exported from the top and they terminate within the body of the top module, ie slave stream has the receive path and produces the stream to the top body with some hand-shake and master stream produces data so it needs to receive the data with some hand-shake. Top module body is where these local interfaces and the hash function lives.

 

>> "0000"    => m00_axis_tstrb,   //Uncertain about this one

 

strb denotes how many bytes are valid in the tdata output. If they're all zeros, it means you are not sending anything out regardless what you your tvalid does.

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dman
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Registered: ‎08-22-2016

Thanks muzaffer,

 

This is what I added to the top file as of now:

 

    // Add user logic here
    wire buffer_dummy;

    keccak # () keccak_0 (
           .clk(s00_axis_aclk),
           .rst_n(s00_axis_aresetn),
           .din(s00_axis_tdata),
           .din_valid(s00_axis_tvalid),
           .ready_at_output(m00_axis_tready),
           .buffer_full(buffer_dummy),
           .ready(s00_axis_tready),
           .dout(m00_axis_tdata),
           .dout_valid(m00_axis_tvalid),
           .last_block(m00_axis_tlast)
           );

    // User logic ends

 

Shouldn't I remove the connections that are connected to the M_AXIS interface ? Otherwise some signals like: m00_axis_tready, m00_axis_tdata, m00_axis_tvalid, ... get driven twice ?

But doing this will disconnect the handshaking in the lower modules, I presume ?

Thanks in advance,

 

Dman

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muzaffer
Teacher
Teacher
10,353 Views
Registered: ‎03-31-2012
It seems like you're implementing the axis master within your IP. In that case you don't need the axis master block anymore. Actually you don't need the axis slave either as you are consuming s00_axis_tvalid/tdata and producing the s00_axis_tready so you have a full slave, compute, master block already.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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