04-17-2014 07:29 AM
Hi forum users,
I would like to know if there is some Users Guides on How to use AXI4-LITE Slave and Master from a custom peripheral create on Vivado.
I don't know which signals I can use into my user_logic.vhd code.
What I want to do is to read datas from another peripheral and use those datas into my user_logic.vhd.
Thanks for your help,
04-17-2014 09:36 AM
There is one XAPP which talks about using Create and Package IP Wizard in Vivado to create IP's with different interfaces
04-17-2014 11:35 PM
04-21-2014 02:01 PM
04-22-2014 12:27 AM
I've created a Custom IP with axi slave and master interfaces so that give me the following picture :
Now I have three files :
HSP_RED_v1.0.vhd is my use_logic.vhd and the two others files are AXI interfaces.
My custom IP receive datas via S00_AXI and do some modifications in HSP_RED_v1.0 then now, what I want is to send those datas from my HSP_RED_v1.0 vhdl code via M00_AXI to another IP. This is what I can not do.
Thanks in advance for your reply,
04-22-2014 01:17 AM
In order to achieve your functionality, you have to edit your user logic.You would have to first instantiate the user HDL in the Master AXI module; pass the parameters/variables which needs to be worked on.
If you want this data to be fed to some other IP; you will have to bring it out (as an output port).
Hope this helps.
04-22-2014 01:55 AM
04-22-2014 02:02 AM
Yes thats right. That should be sufficient.
Basically as per the AXI protocol for it..AWADDR and ARADDR denote the write and read addresses respectively .
You can refer the AXI reference guide for more details on the interfacing.
04-22-2014 02:04 AM
05-03-2015 12:31 AM
Hi, I have read the discuss, and i also have the same puzzle about the Master write founction, would you please share it !
04-01-2016 02:10 AM
Sorry I didn't see your questions.. I apologize. Is it good for you ?
If not, I solved my problem with the use of the registers. I mapped them to my user logic ports which have to receive datas or be read and that works (I'm talking about AXI4 lite, create internal signals and make them external then map to user logic).
For AXI4 burst there are no register for me, I use a FIFO so mapped the entry with the wdata bus and all the others acknowledges signals. I don't use the pre-created function (If there are).
Hope my answer will help you even if it is perhaps a little late...
01-29-2020 06:07 AM
no one can post his VHDL solution (as a running example) to better understand how to modify the AXI_M port code to arrange our own problems?
01-29-2020 06:49 AM
In many cases the answer is no. Many of us work for companies, either as employees, contractors or consultants. The companies consider our work products to be their Intellectual Property. Have you looked at the pdf in the link of one of the posts? Have you tried to build an AXI IP with the integrator tool? Try that, then start a new post with your specific questions. This is a thread that was answered 6 years ago.
01-30-2020 06:42 AM