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Contributor
Contributor
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Registered: ‎02-18-2014

Custom peripheral with AXI4 Master

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Hi forum users,

 

I would like to know if there is some Users Guides on How to use AXI4-LITE Slave and Master from a custom peripheral create on Vivado.

 

I don't know which signals I can use into my user_logic.vhd code.

What I want to do is to read datas from another peripheral and use those datas into my user_logic.vhd.

 

Thanks for your help,

 

Best regards,

 

Jerome.

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Contributor
Contributor
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Registered: ‎02-18-2014

Re: Custom peripheral with AXI4 Master

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: Custom peripheral with AXI4 Master

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Hi,

 

There is one XAPP which talks about using Create and Package IP Wizard in Vivado to create IP's with different interfaces

 

http://www.xilinx.com/support/documentation/application_notes/xapp1168-axi-ip-integrator.pdf

 

--Hem

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Contributor
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Registered: ‎02-18-2014

Re: Custom peripheral with AXI4 Master

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Hi Hem,

Thanks for your reply, now I know how to simulate AXI4 buses, that was hepful for that, but it's not really what I want.

In fact I want my custom IP to comunicate with others AXI4 peripherals via it AXI4 Master but I don't know how to use this bus in my user_logic.vhd.
I would just like to know how, for exemple, a data from counter function in user_logic.vhd can be send to another peripheral via the AXI4 Master.

Tell me if you don't understand,

Thanks in advance for your reply.

Jerome.
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Teacher
Teacher
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Registered: ‎03-31-2012

Re: Custom peripheral with AXI4 Master

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If you want to control an axi slave from your code you need to add axi master interfaces to your block. The existing axi channels are for your slave block which the user_logic.vhd implements. To become a master you need to add new interfaces and control them. So your ip will have a slave axi interface to which the processor talks and a master axi interface which your ip implements. For this new interface, awvalid (as an example) is an output where as on the processor axi interface it was an input to your block.
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Contributor
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Registered: ‎02-18-2014

Re: Custom peripheral with AXI4 Master

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Hi Muzaffer,

 

I've created a Custom IP with axi slave and master interfaces so that give me the following picture :

Custom IP

Now I have three files :

 

Sources

HSP_RED_v1.0.vhd is my use_logic.vhd and the two others files are AXI interfaces.

 

My custom IP receive datas via S00_AXI and do some modifications in HSP_RED_v1.0 then now, what I want is to send those datas from my HSP_RED_v1.0 vhdl code via M00_AXI to another IP. This is what I can not do.

 

Thanks in advance for your reply,

 

Jerome.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2012

Re: Custom peripheral with AXI4 Master

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Hi Jerome,

In order to achieve your functionality, you have to  edit your user logic.You would have to first instantiate the user HDL in the Master AXI module; pass the parameters/variables which needs to be worked on.

If you want this data to be fed to some other IP; you will have to bring it out (as an output port).

 

Hope this helps.

 

Regards

Sikta

 

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Contributor
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Registered: ‎02-18-2014

Re: Custom peripheral with AXI4 Master

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Hi Sikta,

Ok so, if I understood I just have to use M00_AXI signals like m00_axi_araddr in my user_code.vhd as an output port if I want to send addresses ?

Thanks for your help,

Regards.
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2012

Re: Custom peripheral with AXI4 Master

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Hi Jerome,

Yes thats right. That should be sufficient.

Basically as per the AXI protocol for it..AWADDR and ARADDR denote the write and read addresses respectively .

You can refer the AXI reference guide for more details on the interfacing.

 

Regards

Sikta

 

 

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Contributor
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Registered: ‎02-18-2014

Re: Custom peripheral with AXI4 Master

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I'm sorry for this double post, I forgot , I have another question, what is m00_axi_init_axi_txn ? How do I use it ?

Thanks.
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Contributor
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Registered: ‎02-18-2014

Re: Custom peripheral with AXI4 Master

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Adventurer
Adventurer
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Registered: ‎10-17-2014

Re: Custom peripheral with AXI4 Master

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Hi, I have read the discuss, and i also have the same puzzle about the Master write founction, would you please share it !

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Visitor
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Registered: ‎10-24-2015

Re: Custom peripheral with AXI4 Master

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Hi,how do you solve it, can you share it?

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Contributor
Contributor
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Registered: ‎02-18-2014

Re: Custom peripheral with AXI4 Master

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Hi @makon @hit2013,

 

Sorry I didn't see your questions.. I apologize. Is it good for you ?

 

If not, I solved my problem with the use of the registers. I mapped them to my user logic ports which have to receive datas or be read and that works (I'm talking about AXI4 lite, create internal signals and make them external then map to user logic).

For AXI4 burst there are no register for me, I use a FIFO so mapped the entry with the wdata bus and all the others acknowledges signals. I don't use the pre-created function (If there are).

 

Hope my answer will help you even if it is perhaps a little late...

 

Best regards,

 

J.

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Registered: ‎09-09-2019

Re: Custom peripheral with AXI4 Master

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Hi all,

no one can post his VHDL solution (as a running example) to better understand how to modify the AXI_M port code to arrange our own problems?

 

Thanks

Pier

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Registered: ‎06-21-2017

Re: Custom peripheral with AXI4 Master

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In many cases the answer is no.  Many of us work for companies, either as employees, contractors or consultants.  The companies consider our work products to be their Intellectual Property.  Have you looked at the pdf in the link of one of the posts?  Have you tried to build an AXI IP with the integrator tool?  Try that, then start a new post with your specific questions.  This is a thread that was answered 6 years ago. 

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Scholar
Scholar
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Registered: ‎05-21-2015

Re: Custom peripheral with AXI4 Master

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You can find a variety of AXI (both Lite and full) examples on GitHub.  My own can be found here.

Dan

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