The latest AXI DMA product guide PG021 Oct 4, 2017 Version 7.1 still contains the advice on page 72 to set the tail descriptor thus:
Program the Tail Descriptor register with some value which is not a part of the BD chain. Say for example 0x50
However in the tail descriptor register description e.g. page 21 there is the informative note:
Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results
My emphasis in bold.
It appears the core/engine will truncate/align an addess if not properly aligned. That is, programming the TDESC to "for example 0x50" results in the value 0x40- which will most likely be in the chain given the usual separation.
This point is lurking in the post:
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-DMA-Cyclic-BD-not-working/m-p/722784#M18450
I think the wording in the guide should be updated to indicate that a "properly aligned" address that is not in the ring of BDs should be used to program the TDESC register when oeprating in cyclic mode.
