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Observer
Observer
2,224 Views
Registered: ‎06-21-2018

DDR Chip Package delay

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Hi

I'm designing a custom board around ZYNQ 7000 - XC7Z020. In UG933 it is recommended that consider package delay of chips in DDR length matching. I already exported package delay of the ZYNQ chip from Vivado and compensate FPGA package delay in Allegro (My layout software). My question is do I need to look for the delay in DDR chip too?

 

My chosen DDR chip is a 8Gb Micron DDR3 with 96FBGA package. But I can't find any package delay file from Micron webpage. Does it mean Micron chips already matched all package delay internally?

 

Regards,

Bijan

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Scholar
Scholar
2,167 Views
Registered: ‎02-01-2013

That's a mighty interesting question you've got there. I've been involved in quite a few Xilinx DDR3/4 designs, and I'm not 100% sure of the answer myself.

IMHO, based on the dearth of information regarding DDR memory device pin skews, a presumption exists that any skews attributable to differences in package routing among related signals in DDR devices are 1) very small, and 2) implicitly included in the memory-device's external timing requirements. 

Accordingly, internal memory-device skews do not need compensation in PCB routing. (At least, not at the speeds Xilinx chips currently run DDR interfaces.)

-Joe G.

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Teacher
Teacher
2,183 Views
Registered: ‎06-16-2013

Hi @alipiroz1

 

Generally, you don't need to consider the trace length in DDR chip.

Because of DRAM vendors define timing specification at the ball of DDR chip.

 

Best regards,

 

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Scholar
Scholar
2,168 Views
Registered: ‎02-01-2013

That's a mighty interesting question you've got there. I've been involved in quite a few Xilinx DDR3/4 designs, and I'm not 100% sure of the answer myself.

IMHO, based on the dearth of information regarding DDR memory device pin skews, a presumption exists that any skews attributable to differences in package routing among related signals in DDR devices are 1) very small, and 2) implicitly included in the memory-device's external timing requirements. 

Accordingly, internal memory-device skews do not need compensation in PCB routing. (At least, not at the speeds Xilinx chips currently run DDR interfaces.)

-Joe G.

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Observer
Observer
2,137 Views
Registered: ‎06-21-2018

@jg_bdsThanks Joe for clarifing that.

Still It sounds strange for me because why a low-cost ddr package can maintain it's pin delay in a decent range while a high-end chip like ZYNQ-7000 can't. I'm absolutly not a chip designer but I'm just curious about it.

 

Hoping for some Xilinx IC designer to shows up :)

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Observer
Observer
2,134 Views
Registered: ‎06-21-2018

In my DDR chip datasheet I can't find any timing for my package
Datasheet Link
I can't see any other files regrad that on micron webpage

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Scholar
Scholar
2,127 Views
Registered: ‎02-01-2013

DDR3 is generally slower and more forgiving than DDR4. Here's an excerpt from a 366-page DDR4 datasheet I keep lying around:

2019-01-07_7-42-39.jpg

It's safe to assume that these package data are comparable to those for DDR3 devices.

Note the similarity in the "Package Delay" values for Input/output (DQ's) and the DQS signals. It's doubtful that both 'types' of signals would have precisely the same ranges without some effort on the part of Micron to control them. These ranges include PVT; so without explicit, pin-by-pin information otherwise, it's reasonable to assume that for a given device, at a given voltage and a given temperature, the delays for the two types of signals will be fairly the same.

As far as the disparity in package-delay information between FPGA's and DDR devices goes: consider the functions of the pins. A DDR device pin has one and only one function--for the most part. DDR manufacturers could have invested gajillions of dollars in package delays control efforts, and then recovered those costs over the billions of devices sold.  FPGA's, on the other hand, usually have many functions per pin, and many different die/package combinations. There are just so many variables. In this case, it's easier to simply publish precise delay information, and compel designers to compensate for those differences in PCB routing.

-Joe G.

 

 

 

 

Observer
Observer
2,112 Views
Registered: ‎06-21-2018

Thanks Jou. Your explanation completely eliminated my doubt
Thank you for your time, thank you for your invaluable knowlege and thank you for everything.
God Bless!

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