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Anonymous
Not applicable
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DDR2_DQ bus oscillates when using PPC440MC

Greetings!

 

I'll throw this out there for folks to ponder.  I'm using the Xilinx "DDR2 Memory Controller fo PowerPC Processors" (PPC440MC).  With the core instantiated in my design, the DDR2_DQ (data) bus begins to oscillate as soon as a clock is applied to the embedded system.  So much so, in fact, that I suspect the simulataneous switch noise causes the PLL to come unglued.  This is coming right out of a functional reset state, so I don't know who or what is driving the bus at this point.  This is the core that bolts directly onto the PPC440, so I don't have any control over the interconnect (XPS does this automatically).  I'm using the pregenerated ucf for the device (FX100T), package (FF1738), IO banks (13/17/21/25), and data width (72b).  All constraints were met.  Anybody ever seen anything like this before?

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kgorga
Newbie
Newbie
2,350 Views
Registered: ‎10-28-2009

My board does the samething!
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