09-16-2016 10:23 AM
Our project is on the VIVADO 2016.2, x64, part xa7z020clg484-1Q
We are using 32-bit DDR3-1066 for our system, which is proprietary video processing.
We believe that there is a data corruption somewhere on the DDR3 read data path before it makes it to the PL. The cache is dsiabled, and we have no idea what could cause it.
Basically, we have a design with DMA/VDMA cores (our own, not Xilinx), and they all connect to the corresponding HP ports through the Xilinx AXI Interconnect.
Furthermore, we pre-initialize the DDR3 memory with a known pattern and we are reading from this memory. We hooked a chipscope on the very AXI HP interface between the PL (Xilinx AXI Interconnect) and the PS, and we observe data corruption during read. The AXI bursts seem ok as far as the AXI protocol is concerned.
We are reading a big chunk of data of 33,177,600 (0x1FA4000) bytes beginning at the address space 0x05100000, and the data corruption happens already after a few AXI bursts on the HP port (first one is about 6k-7k bytes).
The way the data corrupted is somewhat consistent, i.e. it is the same corrupted value most of the time, but the locations at which the corruption occurs, they are random.
Any help on this is very much appreciated.
Thank you very much
09-16-2016 01:08 PM
09-16-2016 02:19 PM
Thank you for prompt response.
We are initializing the memory through our application utilizing Ethernet -> PS MAC -> PL -> PS DDR3.
However, we can also initialize it through PS. The results are the same.
Note also, that we are reading the CORRECT memory contents if we are using Zynq's console. But it is a different access, i.e. reading a block of data through the console means multiple single data beat access while DMA is using 16-data beat bursts. So we suspect that the issue is somewhere between the DDR3 and the PS to PL boundary, within the PS area.
Any other suggestions? Xilinx.... ?
Thanks again and BR
09-26-2016 06:56 AM
09-29-2016 06:22 AM
01-29-2017 12:57 PM
Actually I have same problem with my zedboard, I didn't understand how did you solve the problem?!
I am writing audio samples received from onboard audio codec to the DDR3 through the AXI-DMA and PS. Up to now, every thing works well and I can see that the data are correctly writen in the memory, I check them by mrd command in xmd console.
But as soon as I read the data during the C program in SDK, the data are corrupted!!! would you please let me know how can I resolve this issue?
12-06-2018 10:52 PM
This is the exact issue we are facing now in our design which uses a Zynq7000 device
The DDR3 access is from PS and when we do a ChipScope on the AXI4 Bus of PS-PL interface and see that some data within a burst (256 words in this case) is getting corrupted. The address increment for each burst is fine, but within the burst of 256 words what we read is data from a different address.
Could you please provide me additional details as how this issue was resolved?
12-07-2018 07:51 AM
Hi Vladislav Muravin,
Thank you for your quick response.
Could you please tell me where we can disable the cache in SW.
Because we checked this option in petalinux but we couldn't find it.
12-07-2018 08:30 AM
There has to be a setting somewhere in your SW. I honestly don't know where as this has been done by one of my SW peers