Can someone tell me please, does the MIG allow write address tranactions to be ahead of write data transactions? I have a master that is capable of doing exactly this, as I believe is legal AXI4 slave behaviour, but then the protocol checker is telling me I have error 32 because BVALID is asserting before either the write address handshake completes, or the write data completes. It is, but BVALID is asserting for write data transaction N, but the write address transaction going on at the same time is transaction N+2. I would have thought that if the 'queue' of write address transactions becomes full, the controller simply keeps AWREADY low until such a time that the queue becomes non-full, and that this is not an error condition. (see first attachment).