DDR4 Memory Interface to PL in Zynq Ultrascale+ MPSoC (Ultra96 FPGA Board)

[tirumal]

I implemented a RISC V SoC on Programmable Logic of Zynq Ultrascale+. Now, I want to interface it with the 2GB LPDDR4 Memory present on the FPGA board.

I did the following steps till now:

• I added IP of Zynq Ultrascale+ in IP Integrator and enabled DDR Controller, enabled the AXI HP0 FPD Interface for which PL  (RISC-V SoC implemented on Logic) is the master and DDR Controller is the slave.
• For AXI HP0 FPD Interface, what clock should I be taking?. The DDR4 Memory is having a requested frequency of 533 MHz. 
• I thought since DDR Memory and SoC implemented on PL are operating on different clock domains, I added AXI Clock Converter between the PL and DDR Controller Interface. Am I thinking right or there is no need for it?
• If AXI Clock Converter is necessary, what will be the clock frequencies of the master and slave interfaces of the converter?

I did the entire design in IP Integrator and generated a block design. I am so confused about clocks and their frequencies for different IPs and Interfaces. Please see it and advise me, if I am doing anything wrong. I am attaching the block design below.

[tirumal]

Can anyone please help me with this?

[dylan]

The AXI HP0 FPD has a clock converter built into it already. Thus you only provide your RISC-V interface clock to the HP0 interface. The clock converter is not necessary. The other side is controlled by the Processing System software for the PS in general.

[joancab]

For AXI HP0 FPD Interface, what clock should I be taking? Typically the 100 or 200 MHz. The AXI clock is unrelated to the DDR itself.

Am I thinking right or there is no need for it? Usually, no need. Your CPU clock just has to drive the AXI with the same clock as the PS AXI (100, 200, typically).