10-30-2020 01:36 AM - edited 10-30-2020 01:52 AM
I implemented a RISC V SoC on Programmable Logic of Zynq Ultrascale+. Now, I want to interface it with the 2GB LPDDR4 Memory present on the FPGA board.
I did the following steps till now:
I did the entire design in IP Integrator and generated a block design. I am so confused about clocks and their frequencies for different IPs and Interfaces. Please see it and advise me, if I am doing anything wrong. I am attaching the block design below.
11-30-2020 10:27 AM
12-01-2020 03:28 AM
For AXI HP0 FPD Interface, what clock should I be taking? Typically the 100 or 200 MHz. The AXI clock is unrelated to the DDR itself.
Am I thinking right or there is no need for it? Usually, no need. Your CPU clock just has to drive the AXI with the same clock as the PS AXI (100, 200, typically).