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tatsuya1
Observer
Observer
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Registered: ‎08-20-2020

DECERR is received

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Hi,

I'm using the AXI master I/F which generated in vivado. I've been tring to read some data from DDR3 memory by a physical address(ARPROT=3'd0).
When a AXI bus is observed using a logic analyzer(ILA) inside FPGA, DECERR is received.
I couldn't understand the reason why DECERR is received.

Conditions:
ZYNQ Processor is driven by Linux.
FPGA: XC7Z020-1CLG400I(Zynq-7000)
Vivado version: 2020.1

Thanks

tatuya1

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DECERR.png
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tatsuya1
Observer
Observer
1,037 Views
Registered: ‎08-20-2020

Hi,

Thank you for your reply.
I'm sorry for lacking in information.
The block design is as follows.
A module named "vga_cnt_top" has an AXI master core. ILA is observing AXI bus between master and interconnect.
When the interconnect is replaced with a smartconnect, behavior changed a little, but smartconnect replies by DECERR.
In my environment, 1G byte memory is mounted. Threfore, it is accessible to the address from 0x00000000 to 0x3fffffff.
In case that the condition for "DECERR" reply is as follows, 2 and 3 aren't applicable I think.

1. Address decode error
2. non-secure transaction
3. FIXED type burst
refer to:
https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-Master-Decerr/m-p/804560#M20933

I don't know why the interconnect recognizes as "Address decode error".
Is there some setting of memory map or something?

By the way, the memory access is possible by an index from the environment of Vitis.

Thanks.

tatsuya1

tatsuya1

block.png

smartconnect.png

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11 Replies
florentw
Moderator
Moderator
1,063 Views
Registered: ‎11-09-2015

HI @tatsuya1 

It might be good to have a view of your design and where you are adding the ILA.

For example, do you have an interconnect or smartconnect. Are you looking before or after the interconnect? Did you try to look on both side to see if this was coming from the interconnect?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tatsuya1
Observer
Observer
1,038 Views
Registered: ‎08-20-2020

Hi,

Thank you for your reply.
I'm sorry for lacking in information.
The block design is as follows.
A module named "vga_cnt_top" has an AXI master core. ILA is observing AXI bus between master and interconnect.
When the interconnect is replaced with a smartconnect, behavior changed a little, but smartconnect replies by DECERR.
In my environment, 1G byte memory is mounted. Threfore, it is accessible to the address from 0x00000000 to 0x3fffffff.
In case that the condition for "DECERR" reply is as follows, 2 and 3 aren't applicable I think.

1. Address decode error
2. non-secure transaction
3. FIXED type burst
refer to:
https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-Master-Decerr/m-p/804560#M20933

I don't know why the interconnect recognizes as "Address decode error".
Is there some setting of memory map or something?

By the way, the memory access is possible by an index from the environment of Vitis.

Thanks.

tatsuya1

tatsuya1

block.png

smartconnect.png

View solution in original post

0 Kudos
tatsuya1
Observer
Observer
1,030 Views
Registered: ‎08-20-2020

Hi,

Thank you for your reply.
I'm sorry for lacking in information.
The block design is as follows.
A module named "vga_cnt_top" has an AXI master core. ILA is observing AXI bus between master and interconnect.
When the interconnect is replaced with a smartconnect, behavior changed a little, but smartconnect replies by DECERR.
In my environment, 1G byte memory is mounted. Threfore, it is accessible to the address from 0x00000000 to 0x3fffffff.
In case that the condition for "DECERR" reply is as follows, 2 and 3 aren't applicable I think.

1. Address decode error
2. non-secure transaction
3. FIXED type burst
refer to:
https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-Master-Decerr/m-p/804560#M20933

I don't know why the interconnect recognizes as "Address decode error".
Is there some setting of memory map or something?

By the way, the memory access is possible by an index from the environment of Vitis.

Thanks.

tatsuya1

block.png

DECERR.png

 

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florentw
Moderator
Moderator
1,008 Views
Registered: ‎11-09-2015

HI @tatsuya1 

Can you share a screenshot of the address editor tab in vivado?

This is what defines the routing for the AXI transactions through the Interconnect/Smartconnect. If you did not define the address range accessible by your custom IP correctly you might get the DECERR


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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tatsuya1
Observer
Observer
973 Views
Registered: ‎08-20-2020

Hi,

Thank you for your quick reply.


The screen shot of "address editor" is the following.
For example, when AXI master of vga_cnt_top accesses a memory address of 0x3f800000-0x3f895fff(614k), how do I set it up?

Thanks.

1.png
2.png
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florentw
Moderator
Moderator
956 Views
Registered: ‎11-09-2015

HI @tatsuya1 

Yes this would be the correct settings. Do you still get the DECERR with that?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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tatsuya1
Observer
Observer
922 Views
Registered: ‎08-20-2020

Hi

Thank you for your reply.

Unfortunately, AXI interconnect still replies by DECERR.

Thanks.

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florentw
Moderator
Moderator
914 Views
Registered: ‎11-09-2015

HI @tatsuya1 

Did you re-generate the BD output products before running the simulation?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tatsuya1
Observer
Observer
850 Views
Registered: ‎08-20-2020

Hi,

> Did you re-generate the BD output products before running the simulation?
Yes, I did.


Finally, my IP could access the memory space.
I think that there was misunderstanding in setting of "Address Editor".
Setting of address space my IP need to access as a "master", I should make it "include"(not exclude).
Is my understanding shown in following figure correct?

Thanks.

question.png
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florentw
Moderator
Moderator
828 Views
Registered: ‎11-09-2015

HI @tatsuya1 

Yes this is correct you need to include the address space


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tatsuya1
Observer
Observer
810 Views
Registered: ‎08-20-2020

Hi, Florent-san

I appreciate your help so far.

I've chosen the best answer by mistake.
I'm sorry for that.

Thanks.

tatsuya1

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